Results 151 to 160 of about 11,328 (210)
Investigation of Noise and Resolution of Magnetic FinFET (MAG-FinFET)
IEEE Sensors JournalKhine Thandar Nyunt Swe +2 more
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A Review of Tunnel Field-Effect Transistors: Materials, Structures, and Applications. [PDF]
Micromachines (Basel)Chen S, An Y, Wang S, Liu H.
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Energy and makespan optimised task mapping in fog enabled IoT application: a hybrid approach. [PDF]
Sci RepTripathy N +4 more
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Integrated 2D multi-fin field-effect transistors. [PDF]
Nat CommunYu M +7 more
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Remote Plasma Selective Silicon Etching Enabled Tunable Sub-Fin Process for Improved Parasitic Bottom Channel Control in Gate-All-Around Nanosheet Field-Effect Transistors. [PDF]
Nanomaterials (Basel)Li J, Gao Y, Zhang DW.
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Comparison of SOI FinFETs and Bulk FinFETs
ECS Transactions, 2009Bulk FinFETs and silicon-on-insulator (SOI) FinFETs were compared in terms of device structure, fundamental characteristics, speed characteristics, model, and application. Bulk FinFETs have shown several advantages over SOI FinFETs while keeping nearly the same scaling-down characteristics as those of SOI FinFETs.
Jong-Ho Lee +3 more
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Indium Gallium Zinc Oxide FinFET Compared with Silicon FinFET
Journal of Nano Research, 2021Indium gallium zinc oxide fin-field effect transistor (IGZO FinFET) characteristics are investigated and then compared with Zinc oxide fin-field effect transistor (ZnO FinFET) and the Silicon fin-field effect transistor (Si FinFET). This was done using 3D simulation. The threshold voltage for Si, ZnO, and IGZO is 0.75 V, 0.30 V and 0.05 V respectively.
Unopa Matebesi, Nonofo M.J. Ditshego
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GC-eDRAM design using hybrid FinFET/NC-FinFET
Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, 2020Gain cell embedded DRAMs (GC-eDRAM) are a potential alternative for conventional static random access memories thanks to their attractive advantages such as high density, low-leakage, and two-ported operation. As CMOS technology nodes scale down, the design of GC-eDRAM at deeply scaled nanometer nodes becomes more challenging.
Ramin Rajaei +4 more
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Proceedings of the 48th Design Automation Conference, 2011
We present CACTI-FinFET, an integrated framework for simulation of power, delay, temperature, as well as process variations of FinFET-based caches. We have developed a FinFET design library and process variation models to characterize the delay and leakage spreads of such caches.
Chun-Yi Lee, Niraj K. Jha
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We present CACTI-FinFET, an integrated framework for simulation of power, delay, temperature, as well as process variations of FinFET-based caches. We have developed a FinFET design library and process variation models to characterize the delay and leakage spreads of such caches.
Chun-Yi Lee, Niraj K. Jha
openaire +1 more source