Results 141 to 150 of about 7,054 (167)

Degradation Induced by Total Ionizing Dose and Hot Carrier Injection in SOI FinFET Devices. [PDF]

Micromachines (Basel)
Yu H, Zhou W, Liu H, Wang S, Chen S, Liu C.   +5 more
europepmc   +1 more source

Effect of C₂H₂F₄/CF₄O with low global warming potentials on SiN_x etching as a CHF₃ replacement. [PDF]

Sci Rep
Kim KL, Hong JW, Jeon YW, Jeong JW, Kim CH, Eoh HJ, Kim SH, Park JS, Cho NI, Kwak JH, Kim Y, Yeom GY.   +11 more
europepmc   +1 more source

An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs. [PDF]

Nat Commun
Pal A, Chai Z, Jiang J, Cao W, Davies M, De V, Banerjee K.   +6 more
europepmc   +1 more source

A Review of Reliability in Gate-All-Around Nanosheet Devices. [PDF]

Micromachines (Basel)
Wang M.
europepmc   +1 more source

Anisotropic exchange interaction of two hole-spin qubits. [PDF]

Nat Phys
Geyer S, Hetényi B, Bosco S, Camenzind LC, Eggli RS, Fuhrer A, Loss D, Warburton RJ, Zumbühl DM, Kuhlmann AV.   +9 more
europepmc   +1 more source

Sub-THz communication systems: pushing the capabilities of silicon. [PDF]

Commun Eng
Gruber J, Alotaibi H, Tabatabavakili A, Chen L, Aghasi H, Naghavi SMH, Afshari E.   +6 more
europepmc   +1 more source

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology. [PDF]

Nanomaterials (Basel)
Radamson HH, Miao Y, Zhou Z, Wu Z, Kong Z, Gao J, Yang H, Ren Y, Zhang Y, Shi J, Xiang J, Cui H, Lu B, Li J, Liu J, Lin H, Xu H, Li M, Cao J, He C, Duan X, Zhao X, Su J, Du Y, Yu J, Wu Y, Jiang M, Liang D, Li B, Dong Y, Wang G.   +30 more
europepmc   +1 more source

Energy-constrained workflow scheduling for DVFS-enabled heterogeneous systems in cloud computing environments. [PDF]

Sci Rep
Ahmad W, Silaparasetti L, Arya P, Pandya S, Kumar P, Khan T, Alabdulatif A.   +6 more
europepmc   +1 more source

Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits

Microelectronic Engineering, 2012
In this paper, a fin-shaped field effect transistor (FinFET) structure which uses ground plane concept is proposed and theoretically investigated. The ground plane reduces the coupling of electric field between the source and drain reducing drain-induced
Mehdi Saremi, Ali Afzali-Kusha, Saeed Mohammadi   +2 more
exaly   +2 more sources

Some of the next articles are maybe not open access.

Related searches:

Analog and RF Performance Evaluation of Junctionless Accumulation Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET

Silicon, 2021
Rishu Chaujar, Bhavya Kumar
exaly