Results 161 to 170 of about 11,359 (209)
Some of the next articles are maybe not open access.
Proceedings of the 48th Design Automation Conference, 2011
We present CACTI-FinFET, an integrated framework for simulation of power, delay, temperature, as well as process variations of FinFET-based caches. We have developed a FinFET design library and process variation models to characterize the delay and leakage spreads of such caches.
Chun-Yi Lee, Niraj K. Jha
openaire +1 more source
We present CACTI-FinFET, an integrated framework for simulation of power, delay, temperature, as well as process variations of FinFET-based caches. We have developed a FinFET design library and process variation models to characterize the delay and leakage spreads of such caches.
Chun-Yi Lee, Niraj K. Jha
openaire +1 more source
CASCODE FINFET DIRECT COUPLED AMPLIFIER USING CADENCE FINFET TECHNOLOGY
2023Abstract A direct-coupled amplifier is a type of electronic amplifier where the output of one amplification stage is directly connected to the input of the next stage without the use of coupling capacitors or transformers. This direct connection allows both DC (direct current) and AC (alternating current) signals to pass from one stage to the next.
V. SHARMILA +5 more
openaire +1 more source
Numerical simulation on novel FinFETs: asymmetric poly-silicon gate FinFETs and TiN gate FinFETs
Journal of Computational Electronics, 2008We report our numerical study on the device performance of an asymmetric poly-silicon gate FinFET and FinFET with TiN metal gate structure. Our numerical simulation revealed that the asymmetric poly-silicon FinFET structure and TiN gate FinFET structures exhibit superior V T tolerance over the conventional FinFET structure with ...
Han-Geon Kim, Taeyoung Won
openaire +1 more source
Driving capability of SG FinFET and IG FinFET
2015 International Conference on Electrical, Electronics, Signals, Communication and Optimization (EESCO), 2015With the downscaling of the MOSFETs it was not possible to further improve the performance of transistors. FinFET provides the best alternative to the classical planar CMOS technology. Because scaling of CMOS technology leads to saturated performance and increased statistical variability.
Ankja Dubey, Sandeep Singh Gill
openaire +1 more source
SOI FinFET versus bulk FinFET for 10nm and below
2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014FinFETs may in principle be built on either bulk [1–3] or SOI [4–5] substrates. In this paper we will review some of the technical issues associated with choice of substrate, directly comparing empirical results on 10nm hardware for which all the other processes are as much the same as possible.
Terence B. Hook +10 more
openaire +1 more source
Unified FinFET compact model: Modelling Trapezoidal Triple-Gate FinFETs
2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2013A unified FinFET compact model is proposed for devices with complex fin cross-sections. It is represented in a normalized form, where only four different model parameters are needed. The proposed model accurately predicts the current-voltage characteristics of different FinFETs structures such as Double-Gate (DG), Cylindrical Gate-All-Around (Cy-GAA ...
Juan Pablo Duarte +4 more
openaire +1 more source
Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs)
IEEE Transactions on Electron Devices, 2007The threshold voltages Vth of the body-tied double/triple-gate MOSFETs (bulk FinFETs) implemented on bulk silicon (Si) wafers were modeled systematically and compared with data obtained from 3-D device simulation. The threshold-voltage behaviors of the bulk FinFETs were modeled, for the first time, based on charge sharing. For the simplified Vth model,
Byung-Kil Choi +4 more
openaire +1 more source
2010 23rd International Conference on VLSI Design, 2010
This paper describes the SRAM design concept in FinFETtechnologies using unique features of non-planar double-gated devices. The parameter space required to design FinFETs is explored.Variety of SRAM design techniques are presented exploiting the advantages of tied gate and independent gate controlled configurations.
Rajiv Joshi, Keunwoo Kim, Rouwaida Kanj
openaire +1 more source
This paper describes the SRAM design concept in FinFETtechnologies using unique features of non-planar double-gated devices. The parameter space required to design FinFETs is explored.Variety of SRAM design techniques are presented exploiting the advantages of tied gate and independent gate controlled configurations.
Rajiv Joshi, Keunwoo Kim, Rouwaida Kanj
openaire +1 more source