Results 261 to 270 of about 21,585 (298)

Verification of the decimal floating-point square root operation

2014 19th IEEE European Test Symposium (ETS), 2014
Decimal floating-point is a relatively recent addition to the IEEE standard (IEEE Std 754-2008). There exist few verification techniques that can check whether software libraries or hardware designs are in compliance with the standard. Our work presents a verification method to verify implementations of the decimal floating-point square root operation.
Amr A. R. Sayed-Ahmed, Hossam A. H. Fahmy, Ulrich Kühne   +2 more
openaire   +1 more source

A re-evaluation of the practicality of floating-point operations on FPGAs

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251), 2002
The use of reconfigurable hardware to perform high precision operations such as IEEE floating point operations has been limited in the past by FPGA resources. We discuss the implementation of IEEE single precision floating-point multiplication and addition.
Walter B. Ligon III, Scott McMillan, Greg Monn, Kevin Schoonover, Fred Stivers, Keith D. Underwood   +5 more
openaire   +1 more source

Computation of numerical algorithms with parametric floating point operators

Journal of Systems Architecture, 1997
Abstract The computation complexity of a large number of applications, makes useful the development of new design strategies both in the direction of correctness and reduction of computational time and size of the used devices. Since a large part of numerical algorithms involves the computation of polynomial expansions in terms of sum and products of
Massimo Bartolucci, Paolo Guazzoni, Giorgio Manfredi, Giacomo R. Sechi, Luisa Zetta   +4 more
openaire   +1 more source

Generation of floating point 2D translation operators for FPGA

2015 IEEE 10th Jubilee International Symposium on Applied Computational Intelligence and Informatics, 2015
This paper presents an FPGA implementation of a matrix operator for geometric two dimensional translation. The generated architecture takes advantage of the particular form of the translation matrix, ignoring the null elements. We have generated architectures for floating point operators of half, simple, double precision.
Ovidiu Sicoe, Alexandru Amaricai, Mircea Popa 0001   +2 more
openaire   +1 more source

Design issues in division and other floating-point operations

IEEE Transactions on Computers, 1997
Floating-point division is generally regarded as a low frequency, high latency operation in typical floating-point applications. However, in the worst case, a high latency hardware floating-point divider can contribute an additional 0.50 CPI to a system executing SPECfp92 applications. This paper presents the system performance impact of floating-point
Stuart F. Oberman, Michael J. Flynn
openaire   +1 more source

Parameterizable floating-point library for arithmetic operations in FPGAs

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes, 2009
Floating-point operations are an essential requisite in a wide range of computational and engineering applications that need good performance and high precision. Current advances in VLSI technology raised the density integration fast enough, allowing the designers to develop directly in hardware several floating-point operations commonly implemented in
Diego F. Sánchez, Daniel M. Muñoz, Carlos H. Llanos, Mauricio Ayala-Rincón   +3 more
openaire   +1 more source

Static Analyses of the Precision of Floating-Point Operations

2001
Computers manipulate approximations of real numbers, called floating-point numbers. The calculations they make are accurate enough for most applications. Unfortunately, in some (catastrophic) situations, the floating-point operations lose so much precision that they quickly become irrelevant.
openaire   +1 more source

Micro-optimization of floating-point operations

Proceedings of the third international conference on Architectural support for programming languages and operating systems, 1989
This paper describes micro-optimization, a technique for reducing the operation count and time required to perform floating-point calculations. Micro-optimization involves breaking floating-point operations into their constituent micro-operations and optimizing the resulting code. Exposing micro-operations to the compiler creates many opportunities for
openaire   +1 more source

A scheme for accelerated floating point operation in small computers

Computers and Biomedical Research, 1970
Abstract A technique has been developed which reduces running time of floating point operations in a PDP-8 by approximately a factor of three. It is equally applicable to other small computers.
openaire   +2 more sources

Gate Array Implementation of On-line Algorithms for Floating-point Operations

1990 Conference Record Twenty-Fourth Asilomar Conference on Signals, Systems and Computers, 1990., 1991
We present gate array designs of on-line arithmetic units for radix-2 floating-point addition, multiplication and division operations. Performance and complexity characteristics of the implementations of on-line arithmetic units are discussed and compared with those of the compatible conventional floating-point algorithms implemented in the same ...
Paul K.-G. Tu, Milos D. Ercegovac
openaire   +1 more source