Results 11 to 20 of about 3,649,820 (385)

The MODUS Approach to Formal Verification [PDF]

open access: yesBusiness Systems Research, 2014
Background: Software reliability is of great importance for the development of embedded systems that are often used in applications that have requirements for safety. Since the life cycle of embedded products is becoming shorter, productivity and quality
Brewka Lukasz   +2 more
doaj   +4 more sources

Formal Modeling and Verification for MVB [PDF]

open access: yesJournal of Applied Mathematics, 2013
Multifunction Vehicle Bus (MVB) is a critical component in the Train Communication Network (TCN), which is widely used in most of the modern train techniques of the transportation system.
Mo Xia   +3 more
doaj   +3 more sources

End-to-End Formal Verification of Ethereum 2.0 Deposit Smart Contract [PDF]

open access: yesComputer Aided Verification32nd International Conference, 2020
We report our experience in the formal verification of the deposit smart contract, whose correctness is critical for the security of Ethereum 2.0, a new Proof-of-Stake protocol for the Ethereum blockchain.
Park D, Zhang Y, Rosu G.
europepmc   +2 more sources

A model-based approach to automation of formal verification of ROS 2-based systems [PDF]

open access: yesFrontiers in Robotics and AI
Formal verification of robotic applications, particularly those based on ROS 2, is desirable for ensuring correctness and safety. However, the complexity of formal methods and the manual effort required for model creation and parameter extraction often ...
Lukas Dust   +4 more
doaj   +2 more sources

Simulator Semantics for System Level Formal Verification [PDF]

open access: yesElectronic Proceedings in Theoretical Computer Science, 2015
Many simulation based Bounded Model Checking approaches to System Level Formal Verification (SLFV) have been devised. Typically such approaches exploit the capability of simulators to save computation time by saving and restoring the state of the system ...
Toni Mancini   +4 more
doaj   +7 more sources

Formal Verification of an Iterative Low-Power x86 Floating-Point Multiplier with Redundant Feedback [PDF]

open access: yesElectronic Proceedings in Theoretical Computer Science, 2011
We present the formal verification of a low-power x86 floating-point multiplier. The multiplier operates iteratively and feeds back intermediate results in redundant representation. It supports x87 and SSE instructions in various precisions and can block
Peter-Michael Seidel
doaj   +4 more sources

An experimental Study using ACSL and Frama-C to formulate and verify Low-Level Requirements from a DO-178C compliant Avionics Project [PDF]

open access: yesElectronic Proceedings in Theoretical Computer Science, 2015
Safety critical avionics software is a natural application area for formal verification. This is reflected in the formal method's inclusion into the certification guideline DO-178C and its formal methods supplement DO-333.
Frank Dordowsky
doaj   +4 more sources

Formal Verification of Neural Network Controlled Autonomous Systems [PDF]

open access: yesInternational Conference on Hybrid Systems: Computation and Control, 2018
In this paper, we consider the problem of formally verifying the safety of an autonomous robot equipped with a Neural Network (NN) controller that processes LiDAR images to produce control actions.
Akintunde M. E.   +10 more
core   +2 more sources

Formal Verification and Co-Simulation in the Design of a Synchronous Motor Control Algorithm

open access: yesEnergies, 2020
Mechatronic systems are a class of cyber-physical systems, whose increasing complexity makes their validation and verification more and more difficult, while their requirements become more challenging.
Cinzia Bernardeschi   +4 more
doaj   +2 more sources

Using LLMs to Facilitate Formal Verification of RTL [PDF]

open access: yesarXiv.org, 2023
Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as SystemVerilog Assertions (SVA), are time-consuming and error-prone to write,
Marcelo Orenes-Vera   +2 more
semanticscholar   +1 more source

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