Results 31 to 40 of about 1,803,900 (290)
USABILITY REQUIREMENT OF FORMAL VERIFICATION TOOLS
Asia-Pacific Journal of Information Technology and Multimedia, 2012 Formal notations employ mathematical symbols and interpretation to illustrate system elements. The formality imposed by the notations allows the accuracy and consistency of a system model to be confirmed by verification tools. Formal notations on
Rozilawati Razali, Paul Garratt
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Survey on Learning-Based Formal Methods: Taxonomy, Applications and Possible Future Directions
IEEE Access, 2020 Formal methods play an important role in testing and verifying software quality, especially in modern society with rapid technological updates.
Fujun Wang +3 more
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Formal Verification of HotStuff
, 2021 HotStuff is a recent algorithm for repeated distributed consensus used in permissioned blockchains. We present a simplified version of the HotStuff algorithm and verify its safety using both Ivy and the TLA Proof Systems tools.We show that HotStuff deviates from the traditional view-instance model used in other consensus algorithms and instead follows ...
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Formal Verification of Synchronizers [PDF]
, 2005 Large Systems on Chips (SoC) comprise multiple clock domains, and inter-domain data transfers require synchronization. Synchronizers may fail due to metastability, but when using proper synchronization circuits the probability of such failures can be made negligible.
Tsachy Kapschitz, Ran Ginosar
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Formal Verification of STPA with Model Checking
Scientific Journal of Gdynia Maritime University, 2023 As technology advances, hardware-centric systems are rapidly moving towards software-centric ones, and their complexity is rapidly increasing. In particular, systems directly related to safety require thorough verification.
Ryeonggu Kwon, Gihwon Kwon
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The MODUS Approach to Formal Verification
Business Systems Research, 2014 Background: Software reliability is of great importance for the development of embedded systems that are often used in applications that have requirements for safety. Since the life cycle of embedded products is becoming shorter, productivity and quality
Brewka Lukasz +2 more
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Formal verification in a commercial setting [PDF]
Proceedings of the 34th annual conference on Design automation conference - DAC '97, 1997 This tutorial addresses the following questions: why do formal verification? who is doing it today? what are they doing? how are they doing it? what about the future?
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Formal Verification of Three-Valued Digital Waveforms
Моделирование и анализ информационных систем, 2019 We investigate a formal verification problem (mathematically rigorous correctness checking) for digital waveforms used in practical development of digital microelectronic devices (digital circuits) at early design stages.
Nina Yu. Kutsak, Vladislav V. Podymov
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Formal verification of a deadlock detection algorithm [PDF]
Electronic Proceedings in Theoretical Computer Science, 2011 Deadlock detection is a challenging issue in the analysis and design of on-chip networks. We have designed an algorithm to detect deadlocks automatically in on-chip networks with wormhole switching.
Freek Verbeek, Julien Schmaltz
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From RT-LOTOS to Time Petri Nets new foundations for a verification platform [PDF]
, 2005 The formal description technique RT-LOTOS has been selected as intermediate language to add formality to a real-time UML profile named TURTLE. For this sake, an RT-LOTOS verification platform has been developed for early detection of design errors in ...
Sadani, Tarek +5 more
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