Results 11 to 20 of about 1,803,900 (290)

Formal Modeling and Verification for MVB [PDF]

open access: yesJournal of Applied Mathematics, 2013
Multifunction Vehicle Bus (MVB) is a critical component in the Train Communication Network (TCN), which is widely used in most of the modern train techniques of the transportation system.
Mo Xia   +3 more
doaj   +3 more sources

Simulator Semantics for System Level Formal Verification [PDF]

open access: yesElectronic Proceedings in Theoretical Computer Science, 2015
Many simulation based Bounded Model Checking approaches to System Level Formal Verification (SLFV) have been devised. Typically such approaches exploit the capability of simulators to save computation time by saving and restoring the state of the system ...
Toni Mancini   +4 more
doaj   +3 more sources

Methodology for the formal specification of RTL RISC processor designs (with particular reference to the ARM6) [PDF]

open access: yes, 2003
Due to the need to meet increasingly challenging objectives of increasing performance, reducing power consumption and reducing size, synchronous processor core designs have been increasing significantly in complexity for some time now.
Schostak, Daniel Paul
core   +7 more sources

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022 [PDF]

open access: yes, 2022
The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification.

core   +2 more sources

Coverage Metrics for Formal Verification [PDF]

open access: yesInternational Journal on Software Tools for Technology Transfer, 2003
In formal verification, we verify that a system is correct with respect to a specification. Even when the system is proven to be correct, there is still a question of how complete the specification is, and whether it really covers all the behaviors of the system.
Hana Chockler   +2 more
openaire   +4 more sources

FIVER – Robust Verification of Countermeasures against Fault Injections

open access: yesTransactions on Cryptographic Hardware and Embedded Systems, 2021
Fault Injection Analysis is seen as a powerful attack against implementations of cryptographic algorithms. Over the last two decades, researchers proposed a plethora of countermeasures to secure such implementations.
Jan Richter-Brockmann   +4 more
doaj   +1 more source

Formal verification of an ARM processor [PDF]

open access: yesProceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), 1999
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM processors, uses features such as a 5-stage instruction pipeline, predicated execution, forwarding logic and multi-cycle instructions. The instruction set of the processor was
Vishnu A. Patankar   +2 more
openaire   +1 more source

Formal Verification of Websites

open access: yesElectronic Notes in Theoretical Computer Science, 2008
AbstractIn this paper, a model for websites is presented. The model is well-suited for the formal verification of dynamic as well as static properties of the system. A website is defined as a collection of web pages which are semantically connected in some way. External web pages (which are related pages not belonging to the website) are treated as the
Sonia Flores   +2 more
openaire   +1 more source

Temporal verification in secure group communication system design [PDF]

open access: yes, 2007
The paper discusses an experience in using a real-time UML/SysML profile and a formal verification toolkit to check a secure group communication system against temporal requirements.
Villemur, Thierry   +7 more
core   +1 more source

Proceedings of the 21st Conference on Formal Methods in Computer-Aided Design – FMCAD 2021 [PDF]

open access: yes, 2021
The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification.

core   +1 more source

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