Results 11 to 20 of about 129,094 (257)

Coverage Metrics for Formal Verification [PDF]

open access: yesInternational Journal on Software Tools for Technology Transfer, 2003
In formal verification, we verify that a system is correct with respect to a specification. Even when the system is proven to be correct, there is still a question of how complete the specification is, and whether it really covers all the behaviors of the system.
Hana Chockler   +2 more
openaire   +2 more sources

Formal verification for a PMQTT protocol

open access: yesEgyptian Informatics Journal, 2020
The future of Internet of Things (IoT) foresees a world of interconnected people with every physical object in a seamless manner. The security related aspects for the IoT world are still an open field of discussion and research.
Eman Elemam   +3 more
doaj   +1 more source

Formal verification of an ARM processor [PDF]

open access: yesProceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), 1999
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM processors, uses features such as a 5-stage instruction pipeline, predicated execution, forwarding logic and multi-cycle instructions. The instruction set of the processor was
Vishnu A. Patankar   +2 more
openaire   +1 more source

FIVER – Robust Verification of Countermeasures against Fault Injections

open access: yesTransactions on Cryptographic Hardware and Embedded Systems, 2021
Fault Injection Analysis is seen as a powerful attack against implementations of cryptographic algorithms. Over the last two decades, researchers proposed a plethora of countermeasures to secure such implementations.
Jan Richter-Brockmann   +4 more
doaj   +1 more source

Context-aware approach for formal verification

open access: yesEAI Endorsed Transactions on Context-aware Systems and Applications, 2016
The Context-aware approach has proven to be an effective technique for software model-checking verification. It focuses on the explicit modelling of environment as one or more contexts.
Amel Benabbou   +2 more
doaj   +1 more source

Formal Verification of a Hybrid IoT Operating System Model

open access: yesIEEE Access, 2021
The Internet of Things (IoT) is becoming an increasingly common paradigm. As IoT usage scenarios have increased, many challenges in IoT operating systems’ safety and adaptability have remained.
Yuqian Guan, Jian Guo, Qin Li
doaj   +1 more source

Formal Verification of an Iterative Low-Power x86 Floating-Point Multiplier with Redundant Feedback [PDF]

open access: yesElectronic Proceedings in Theoretical Computer Science, 2011
We present the formal verification of a low-power x86 floating-point multiplier. The multiplier operates iteratively and feeds back intermediate results in redundant representation. It supports x87 and SSE instructions in various precisions and can block
Peter-Michael Seidel
doaj   +1 more source

Formal Verification of Websites

open access: yesElectronic Notes in Theoretical Computer Science, 2008
AbstractIn this paper, a model for websites is presented. The model is well-suited for the formal verification of dynamic as well as static properties of the system. A website is defined as a collection of web pages which are semantically connected in some way. External web pages (which are related pages not belonging to the website) are treated as the
Sonia Flores   +2 more
openaire   +1 more source

Formal Verification of the FDO Protocol

open access: yes2023 IEEE Conference on Standards for Communications and Networking (CSCN), 2023
Fido Device Onboarding (FDO) by the FIDO Alliance is expected to become the leading standard protocol for device secure onboarding. It is automatic, plug&play and it enables late binding. It overcomes the problems related to both proprietary zero-touch protocols and the traditional manual approach.
Simone Bussa   +2 more
openaire   +2 more sources

A Specification-Based Semi-Formal Functional Verification Method by a Stage Transition Graph Model

open access: yesIEEE Access, 2019
The semi-formal verification method, in which the functionality is formally specified and the checking is undertaken through the formal model-based simulation, has been a promising choice for the functional verification of hardware designs.
Zhao Lv   +3 more
doaj   +1 more source

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