Results 31 to 40 of about 117,504 (308)
The MODUS Approach to Formal Verification
Business Systems Research, 2014 Background: Software reliability is of great importance for the development of embedded systems that are often used in applications that have requirements for safety. Since the life cycle of embedded products is becoming shorter, productivity and quality
Brewka Lukasz +2 more
doaj +1 more source
Formal Verification of Three-Valued Digital Waveforms
Моделирование и анализ информационных систем, 2019 We investigate a formal verification problem (mathematically rigorous correctness checking) for digital waveforms used in practical development of digital microelectronic devices (digital circuits) at early design stages.
Nina Yu. Kutsak, Vladislav V. Podymov
doaj +1 more source
Formal Verification of Language-Based Concurrent Noninterference
Journal of Formalized Reasoning, 2013 We perform a formal analysis of compositionality techniques for proving possibilistic noninterference for a while language with parallel composition.
Andrei Popescu +2 more
doaj +1 more source
Formal verification of a deadlock detection algorithm [PDF]
Electronic Proceedings in Theoretical Computer Science, 2011 Deadlock detection is a challenging issue in the analysis and design of on-chip networks. We have designed an algorithm to detect deadlocks automatically in on-chip networks with wormhole switching.
Freek Verbeek, Julien Schmaltz
doaj +1 more source
Formal Modelling and Runtime Verification of Autonomous Grasping for Active Debris Removal
Frontiers in Robotics and AI, 2022 Active debris removal in space has become a necessary activity to maintain and facilitate orbital operations. Current approaches tend to adopt autonomous robotic systems which are often furnished with a robotic arm to safely capture debris by identifying
Marie Farrell +4 more
doaj +1 more source
Formal Modeling and Verification for MVB
Journal of Applied Mathematics, 2013 Multifunction Vehicle Bus (MVB) is a critical component in the Train Communication Network (TCN), which is widely used in most of the modern train techniques of the transportation system.
Mo Xia +3 more
doaj +1 more source
FVM: A Formal Verification Methodology for VHDL Designs
IEEE Open Journal of the Computer SocietyWith the increasing complexity of digital designs, functional verification is becoming unmanageable. Bugs that survive verification cause a number of issues with functional, performance, security, safety and economic impact, and are unfortunately ...
Hipolito Guzman-Miranda +2 more
doaj +1 more source
Towards Evaluating Size Reduction Techniques for Software Model Checking [PDF]
Electronic Proceedings in Theoretical Computer Science, 2017 Formal verification techniques are widely used for detecting design flaws in software systems. Formal verification can be done by transforming an already implemented source code to a formal model and attempting to prove certain properties of the model (e.
Gyula Sallai +3 more
doaj +1 more source
PROMELA based formal verification for safety-critical software
Xibei Gongye Daxue Xuebao, 2022 聚焦安全关键软件, 研究基于PROMELA形式模型验证C程序中违反断言、数组越界、空指针解引用、死锁及饥饿等5类故障技术。建立C程序抽象语法树节点到PROMELA模型, 验证属性相关函数到PROMELA模型的2类映射规则; 根据映射规则提出由C程序自动生成PROMELA形式模型的算法, 并对算法进行理论分析; 针对C程序中5种故障类型, 分别给出基于PROMELA模型的形式化验证方法, 并分析验证的范围; 覆盖各类故障的验证范围, 为每类故障类型选取12个C程序案例进行实证研究 ...
XING Liang +3 more
doaj +1 more source
Sickle Cell Disease Is an Inherent Risk for Asthma in a Sibling Comparison Study
Pediatric Blood &Cancer, EarlyView.ABSTRACT Introduction Sickle cell disease (SCD) and asthma share a complex relationship. Although estimates vary, asthma prevalence in children with SCD is believed to be comparable to or higher than the general population. Determining whether SCD confers an increased risk for asthma remains challenging due to overlapping symptoms and the ...
Suhei C. Zuleta De Bernardis +9 more
wiley +1 more source