SpChipADF: An Architecture Design Framework for Radar Signal Processing Hardware Accelerators. [PDF]
Wang H +8 more
europepmc +1 more source
A parallel magnetic tunnel junction-based probabilistic Ising processor for efficient quadratic optimization. [PDF]
Yang S +4 more
europepmc +1 more source
An Open-Source QAM MODEM for Visible Light Communication in FPGA for Real-Time Applications. [PDF]
Ricci S.
europepmc +1 more source
Design of a High Dynamic Range Acquisition System for Airborne VNIR Push-Broom Hyperspectral Camera. [PDF]
Feng H, Wang Y, He D, Zhang C, Li C.
europepmc +1 more source
Low power reprogrammable DNA basecaller with an efficient HMM accelerator for real time nanopore sequencing. [PDF]
Shahraki AS +3 more
europepmc +1 more source
Characterization of a Spiking Convolutional Processor for FPGA. [PDF]
Curra-Sosa DA +2 more
europepmc +1 more source
Towards the transformation of MATLAB models into FPGA-Based hardware accelerators. [PDF]
Bal S.
europepmc +1 more source
High-Speed Detection of X-ray Pulses Using a Digital Counter Coupled with Perovskite Composite Scintillators. [PDF]
Khaliq S +8 more
europepmc +1 more source
本发明公开了一种LUT4、FPGA逻辑单元和FPGA逻辑块。该4输入查找表LUT4包括:两个3输入查找表LUT3和四个2选1多路复用器,该两个LUT3为C-LUT3和S-LUT3,该四个2选1多路复用器为FMUX,CMUX,SMUX和F4MUX;数据输入端口A0,A1,以及A2(0)经过CMUX选择后的输出分别进入C-LUT3的三个输入端口;数据输入端口A0,A1(0)与A3(1)经过SMUX选择后的输出,以及A2(0)经过CMUX选择后的输出分别进入S-LUT3的三个输入端口 ...
韩小炜, 陈陵都
core
Application and Comparison of FPGA-Based Carry Chain TDC and DDMTD Schemes in High-Precision Time Synchronization. [PDF]
Huang Y, Yu J, Xia W, Guo Q, Huang L.
europepmc +1 more source

