Results 191 to 200 of about 35,500 (242)

FPGA Implementation ofFDTD Algorithm

2005 Asia-Pacific Microwave Conference Proceedings, 2006
We examined the implementation of the FDTD algorithm to a Field Programmable Gate Array (FPGA) to accelerate an electromagnetic field simulation. We evaluate the calculation error of a fixed-point arithmetic using the FDTD method and show that the error of less than 0.01 is achieved when the bit length is greater than 28 bits. This paper investigates a
H. Suzuki, Y. Takagi, R. Yamaguchi, S. Uebayashi   +3 more
openaire   +1 more source

FPGA FFT implementation

2010 East-West Design & Test Symposium (EWDTS), 2010
We consider FPGA design flow with C/C++ to Verilog translation and verification and report on FPGA implementation of fast Fourier transform and Wiener filter for noise reduction of speech signals on Xilinx Virtex-4.
S. O. Churayev, B. T. Matkarimov
openaire   +1 more source

Implementing OCR on FPGA

IET-UK International Conference on Information and Communication Technology in Electrical Sciences (ICTES 2007), 2007
Character recognition systems have contributed tremendously to the automation of data entry process. Many systems are present in software for character recognition. Digital signal processing has traditionally been done using enhanced microprocessors. While the high volume of generic product provides a low cost solution, its performance fall seriously ...
R.P. Ghugardare, S.P. Narote
openaire   +1 more source

FPGA implementation of SVPWM

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013
High performance motor controllers usually require complex operations and long computation time, which makes the implementation task more complex. The PWM signal generator is a key element in ac drives. This paper presents implementation on FPGA of a Space Vector Pulse Width Modulation (SVPWM) using Hardware Description Language VHDL and its co ...
Salim Boukaka, Hicham Chaoui, Pierre Sicard   +2 more
openaire   +1 more source

FPGA implemented decimating filter

28th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2005., 2005
This paper describes the synthesis and the implementation of a digital decimating filter for an ultrasonic beamformer, which uses delta sigma modulators to acquire the received ultrasonic signals. For conventional ultrasonic imaging systems this high-order filter can be very long and complicated and consume a fair amount of power because only one such ...
I. Lie, M.E. Tanase, H.C. Carstea, A. Avram, B. Marinca   +4 more
openaire   +1 more source

Graph Coverage: An FPGA-targeted implementation

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2013
Classification systems specifically designed to deal with fully labeled graphs are gaining importance in many application fields. The main computational bottleneck in such systems is the dissimilarity measure between pairs of graphs. In this paper we propose to accelerate in hardware such computations, relying on the Graph Coverage as the core inexact ...
CINTI, ALESSANDRO, RIZZI, Antonello
openaire   +2 more sources

FPGA Implementation of Log-polar Mapping

2008 15th International Conference on Mechatronics and Machine Vision in Practice, 2008
Log-polar or spatially variant image representation is an important component of active vision system in tracking process for many robotic applications due to its data compression ability, faster sampling rates and hence, direct to faster image-processing speed in machine vision system. In this paper, we try to implement log-polar mapping techniques on
Wong, W.K., Choo, C.W., Loo, C.K., Teh, J.P.   +3 more
openaire   +1 more source

FPGA implementation of IEEE 802.15.3c receiver

2012 IEEE 16th International Symposium on Consumer Electronics, 2012
This paper presents the implementation of the OFDM demodulator and the Viterbi decoder, proposed as part of a wireless High Definition video receiver to be integrated in an FPGA. These blocks were implemented in a Xilinx Virtex-6 FPGA. The complete system was previously modeled and simulated using MATLAB/Simulink to extract important hardware ...
Véstias, Mário, Sarmento, Helena
openaire   +2 more sources

FPGA Implementations of Neocognitrons

2006
In this chapter it is described the implementation of an artificial neural network in a reconfigurable parallel computer architecture using FPGA’s, named Reconfigurable Orthogonal Memory Multiprocessor (REOMP), which uses p 2 memory modules connected to p reconfigurable processors, in row access mode, and column access mode.
Alessandro Noriaki Ide, José Hiroki Saito   +1 more
openaire   +1 more source

Hough transform algorithm for FPGA implementation

2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528), 2001
In this paper a novel algorithm for computing the Hough transform is introduced. The basic idea consists in using a combination of an incremental method with the usual Hough transform expression to join circuit performances and accuracy requirements. The algorithm is primarily developed to fit field programmable gate arrays (FPGA) implementation that ...
Tagzout, Samir, Achour, Karim, Djekoune, Oualid   +2 more
openaire   +2 more sources