Results 201 to 210 of about 35,500 (242)

MIMO Implementation Using FPGA

2017
In the preceding Part 2, RF Wireless On-Body Sensor Designs the physical layer development of the RF/microwave on-body sensor was developed from the scratch.
Nemai Chandra Karmakar, Yang Yang, Abdur Rahim   +2 more
openaire   +1 more source

On the FPGA implementation of empirical mode decomposition algorithm using FPGA

2013 21st Signal Processing and Communications Applications Conference (SIU), 2013
In this paper a single chip hardware architecture for empirical mode decomposition is proposed and implemented on a consumer grade FPGA device. Implementing EMD on a single chip dramatically decreases hardware costs and increases real time processing performance.
ÇELEBİ, ANIL, Kose, Ihsan
openaire   +2 more sources

FPGA implemented reduced Ethernet MAC

2013 IEEE 4th International Conference on Cognitive Infocommunications (CogInfoCom), 2013
This paper presents an implementation of a reduced Ethernet MAC. The reduced MAC is simple and not resource wasteful. Therefore it is suitable to every project which includes network communication. It is especially useful to low performance FPGAs. In practice, the FPGA boards are well applicable to implement network protocols because the implemented ...
Jozsef Suto, Stefan Oniga
openaire   +1 more source

FPGA and Mixed FPGA-DSP Implementations of Electrical Drive Algorithms

2002
This paper deals with the implementation of control algorithms for alternative current (ac) motors using co-design methodology for hard or mixed hardware/software solutions. The authors focus on the design flow and experiments using FPGA / DSP platform. A full FPGA implementation of the well-known field oriented control strategy is presented. In a next
Calmon, F., Fathallah, M., Viverge, Pierre-Jean, Gontrand, C., Carrabina, J., Foussier, P.   +5 more
openaire   +2 more sources

FPGA implementation of hardware voter

5th International Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Service. TELSIKS 2001. Proceedings of Papers (Cat. No.01EX517), 2002
In this paper hardware structure of voting unit for mid-value selection is presented. In the process of the hardware design it is very important to regulate the operation of control logic, especially when it is separated into several independent blocks. This paper shows the manner of hardware mid-value select architecture (HMVSA) control logic coupling.
M.D. Krstic, M.K. Stojcev
openaire   +1 more source

Implementing image applications on FPGAs

Object recognition supported by user interaction for service robots, 2003
The Cameron project has developed a language and compiler for mapping image-based applications to field programmable gate arrays (FPGAs). The paper tests this technology on several applications and finds that FPGAs are between 8 and 800 times faster than comparable Pentiums for image based tasks.
B.A. Draper, J.R. Beveridge, A.P.W. Bohm, C. Ross, M. Chawathe   +4 more
openaire   +1 more source

LDPC decoder implementation using FPGA

2016 8th International Symposium on Telecommunications (IST), 2016
This paper presents a partial-parallel LDPC decoder based on sum-product algorithm with high throughput. The hardware implementation of decoder considers design issues with respect to FPGA and time scheduling is proposed based on modified TPMP1 algorithm in order to reduce the number of clock cycles, hardware resources and power.
Mahdie Kiaee, Hossein Gharaee, Naser Mohammadzadeh   +2 more
openaire   +1 more source

FPGA implementation of SVPWM approximation

2015 Conference on Design of Circuits and Integrated Systems (DCIS), 2015
The PWM signal generator is a key element in DC-AC conversion and AC drives. A new scheme based on the approximation of Space Vector Pulse Width Modulation is proposed to minimize the mathematical complexity involved with the SVPWM, while retaining its advantages. The proposition has been implemented on FPGA using Hardware Description Language VHDL and
Salim Boukaka, Daniel Massicotte, Pierre Sicard   +2 more
openaire   +1 more source

Stack Game – Fpga Implementation

2020
The main goal of this work was to design simplified version of Stack game in VHDL language and implementation to FPGA development kit Spartan-3. There is standard computer keyboard connected via PS/2 interface as input and monitor with VGA interface as output. It was necessary to design 21bit VGA convertor for this project.
openaire   +1 more source