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Phase-Locked Loop Frequency Synthesizers
1998The indirect or phase-locked loop frequency synthesizer offers the distinct advantage over other types of synthesizers of possible low-cost IC integration. This is the main reason why almost all mobile communication chip sets use this circuit. But of course there are also some disadvantages, which require careful study and proper design. Two main areas
J. Craninckx, M. Steyaert
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Simulation of phase-locked loops in phase-frequency domain
2012 IV International Congress on Ultra Modern Telecommunications and Control Systems, 2012This article is devoted to simulation of classical phase-locked loop (PLL). Based on new analytical method for computation of phase detector characteristics (PD), an realization in Simulink for simulation of classical PLL in phase space for general types of signal waveforms is done. This enables to avoid a number of numerical problems in the simulation
Nikolay V. Kuznetsov +5 more
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A Digital Frequency-Locked Loop System for Capacitance Measurement
IEEE Transactions on Instrumentation and Measurement, 2013Similar to phase-locked loops, frequency-locked loops (FLLs) are useful in many applications involving waveform synchronization or synthesis. Simple logic circuit-based relaxation oscillators convert capacitance to frequency, which is a characteristic inverse relationship between output frequency and input capacitance.
Robert Neal Dean, Aditi Kiran Rane
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Frequency Multiplier using Phase-Locked Loop
2020 IEEE 17th India Council International Conference (INDICON), 2020A Phase-Locked Loop (PLL) Frequency multiplier application is been presented in this paper. The designed PLL is a type-2, order-3 CPPLL with a tuning range of 143-176M Hz with the center frequency of 160M Hz and a loop bandwidth of 2M Hz. The functional blocks of the PLL Frequency multiplier include PFD, Charge Pump with a loop filter, a voltage ...
Harish G Shettar +5 more
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Improving the Design of Frequency Lock Loops for GNSS Receivers
IEEE Transactions on Aerospace and Electronic Systems, 2012An analysis of the design and performance of the discrete-update GNSS frequency lock loop (FLL) is presented. Expressions for the design and the steady-state performance of one first-order and two second-order FLL loop filters are developed. Transient performance of the FLL in the presence of thermal noise is examined and the relative performance of ...
James T. Curran +2 more
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Design of delay-locked loop for wide frequency locking range
2013 International SoC Design Conference (ISOCC), 2013In order to increase the frequency locking range, a delay-locked loop (DLL) circuit with frequency to voltage converter (FVC) and phase select circuit is described. For the low power dissipation consideration, the circuit’s bias current is keep at lower level.
Hsun-Hsiang Chen +2 more
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IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics Society, 2012
This paper proposes a new three-phase software phase-locked loop (SPLL) which operates fast and accurately in unbalanced, polluted and frequency deviated circumstances. This new proposed SPLL consists of frequency-locked loop (FLL) and initial phase angle detection PLL. The FLL employs differential algorithm to detect frequency error which could immune
Liang Wang, Qirong Jiang, Lucheng Hong
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This paper proposes a new three-phase software phase-locked loop (SPLL) which operates fast and accurately in unbalanced, polluted and frequency deviated circumstances. This new proposed SPLL consists of frequency-locked loop (FLL) and initial phase angle detection PLL. The FLL employs differential algorithm to detect frequency error which could immune
Liang Wang, Qirong Jiang, Lucheng Hong
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A Sub-Sampling Phase-Locked Loop With a Robust Agile-Locking Frequency-Locked Loop
2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), 2023Chia-Min Chen +2 more
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Automatic NMR field-frequency lock—pulsed phase locked loop approach
Review of Scientific Instruments, 1978A self-contained deuterium frequency-field lock scheme for a high-resolution NMR spectrometer is described. It is based on phase locked loop techniques in which the free induction decay signal behaves as a voltage-controlled oscillator. By pulsing the spins at an offset frequency of a few hundred hertz and using a digital phase-frequency discriminator ...
S, Kan +4 more
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An Integrated Heterodyne Optical Phase-locked Loop with Record Offset Locking Frequency
Optical Fiber Communication Conference, 2014A highly-integrated optical phase-locked loop (OPLL) is realized by photonic and electronic integration. The experiment shows the full functionality of this heterodyne OPLL and 25 GHz offset locking frequency is achieved.
Mingzhi Lu +5 more
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