Results 151 to 160 of about 6,749 (208)

A Critical Examination of Frequency-Fixed Second-Order Generalized Integrator-Based Phase-Locked Loops

open access: yesIEEE Transactions on Power Electronics, 2017
The implementation of a large number of single-phase phase-locked loops (PLLs) involves creating a fictitious quadrature signal. A popular approach for this purpose is using a second-order generalized integrator-based quadrature signal generator (SOGIQSG)
Saeed Golestan   +2 more
exaly   +2 more sources

Asynchronously Controlled Frequency Locked Loop

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2016
A frequency-locked loop (FLL) system typically employs synchronous digital counters to estimate the frequency discrepancy between the output of a local oscillator and an external reference clock. We present a novel FIFO-based frequency detector as an alternative to such counters.
Suwen Yang   +2 more
openaire   +1 more source

A reconfigurable high-frequency phase-locked loop

Proceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412), 2004
Reconfigurable phase-locked loops (PLLs) present the advantage of fast-frequency acquisition combined with narrow-noise bandwidth, since their parameters can be dynamically adjusted. High-frequency PLLs are generally implemented by means of analog circuits which are not easily reconfigured during operation.
Fernando Rangel de Sousa, Bernard Huyart
openaire   +1 more source

Single-Phase Frequency-Locked Loops: A Comprehensive Review

open access: yesIEEE Transactions on Power Electronics, 2019
Synchronization techniques can be classified into open-loop and closed-loop methods. In power and energy applications, which are the focus here, the latter type is more popular.
Saeed Golestan   +2 more
exaly   +2 more sources

A 50 MHz phase- and frequency-locked loop

IEEE Journal of Solid-State Circuits, 1979
A monolithic phase/frequency-locked loop has been developed for operation at up to 50 MHz. The loop combines wide capture range and narrow bandwidth, making it ideal for timing recovery in digital transmission systems. The 24-pin device features an electronically-tuned voltage-controlled LC oscillator and includes the input differentiation and full ...
R. Cordell   +3 more
openaire   +1 more source

A Fractional Frequency Synthesizer Using Frequency Locked Loop

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007
This paper presents a new architecture for wideband fractional frequency synthesizer. The architecture is based on frequency locked loop (FLL). Fractional division is implemented in this FLL by using two feedback loops which are having different frequency division ratio N and N+1.
A. V. Rejeesh, Pradip Mandal
openaire   +1 more source

High-Order Frequency-Locked Loops: A Critical Analysis

open access: yesIEEE Transactions on Power Electronics, 2017
In very recent years, some attempts for designing high-order frequency-locked loops (FLLs) have been made. Nevertheless, the advantages and disadvantages of these structures, particularly in comparison with a standard FLL and high-order phase-locked ...
Saeed Golestan   +2 more
exaly   +2 more sources

Frequency measurement using a frequency locked loop

2011 IEEE Energy Conversion Congress and Exposition, 2011
A phase locked loop method is proposed for fast estimation of utility grid frequency, for control and protection purposes in grid-connected power converters. Using a second order generalized integrator (SOGI) and a ‘novel’ frequency locked loop (nFLL), which makes the SOGI frequency adaptive, the proposed SOGI-nFLL detects small and large step changes ...
Zijun Luo   +3 more
openaire   +1 more source

A digitally-assisted electrothermal frequency-locked loop

2009 Proceedings of ESSCIRC, 2009
A digitally-assisted electrothermal frequency-locked loop (FLL) is presented, whose output frequency is determined by the temperature-dependent thermal diffusivity of bulk silicon. In contrast to previous work, its noise bandwidth is defined by a digital, rather than an analog, filter.
S. Mahdi Kashmiri, Kofi A. A. Makinwa
openaire   +1 more source

An alias-locked loop frequency synthesis architecture

2008 IEEE International Symposium on Circuits and Systems, 2008
This paper presents a phase-locked loop (PLL) using an aliasing divider, referred to as an alias-locked loop (ALL). The ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider in the feedback path.
Leendert van den Berg, Duncan G. Elliott
openaire   +1 more source

Home - About - Disclaimer - Privacy