Results 141 to 148 of about 149 (148)
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ICM 2000. Proceedings of the 12th International Conference on Microelectronics. (IEEE Cat. No.00EX453), 2002
A novel gain- and offset-compensated (GOC) very large time constant (VLT) switched-capacitor (SC) integrator is presented and compared with the previously proposed Nagaraj-89 GOC VLT integrator in terms of gain error, phase error and offset voltage error. The effectiveness of the new integrator is demonstrated by designing a 60 Hz notch filter.
N.A. Radev, K.P. Ivanov
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A novel gain- and offset-compensated (GOC) very large time constant (VLT) switched-capacitor (SC) integrator is presented and compared with the previously proposed Nagaraj-89 GOC VLT integrator in terms of gain error, phase error and offset voltage error. The effectiveness of the new integrator is demonstrated by designing a 60 Hz notch filter.
N.A. Radev, K.P. Ivanov
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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360), 2003
This paper proposes an optimum design of a high frequency Switched-Capacitor IIR interpolation filter for Direct Digital Frequency Synthesizer systems. The circuit is formed by the combination of novel double sampling recursive direct-form II and non-recursive polyphase structures embedding mismatch-free analog delay lines with accurate, wideband gain-
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This paper proposes an optimum design of a high frequency Switched-Capacitor IIR interpolation filter for Direct Digital Frequency Synthesizer systems. The circuit is formed by the combination of novel double sampling recursive direct-form II and non-recursive polyphase structures embedding mismatch-free analog delay lines with accurate, wideband gain-
null Seng-Pan U +3 more
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2004
A gain- and offset- compensated switched-capacitor integrator based on the Simpson's integration method is presented Analytical expressions for the gain, phase and offset voltage errors are derived and compared with the corresponding errors of the earlier one uncompensated integrator.
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A gain- and offset- compensated switched-capacitor integrator based on the Simpson's integration method is presented Analytical expressions for the gain, phase and offset voltage errors are derived and compared with the corresponding errors of the earlier one uncompensated integrator.
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A 3.125Gb/s limit amplifier with 42dB gain and 1μs offset compensation in 0.18μm CMOS
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005., 2005E. Crain, M. Perrott
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2003
Two gain- and offset- compensated two-phase switched-;apacitor integrators based on the second-order Adams-Bashworth's ntegration method are presented. Analytical expressions for the gain, phase ind offset voltage errors are derived and compared with the corresponding errors of the earlier ones uncompensated integrators.
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Two gain- and offset- compensated two-phase switched-;apacitor integrators based on the second-order Adams-Bashworth's ntegration method are presented. Analytical expressions for the gain, phase ind offset voltage errors are derived and compared with the corresponding errors of the earlier ones uncompensated integrators.
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