Results 1 to 10 of about 130,866 (198)
Drift in switched-capacitor integrators
Microelectronics Journal, 1984 Imperfections in MOS devices which cause drift over time in the output voltage of a switched-capacitor integrator include junction leakage, offset voltages, charge pumping, and charge-injection (clock feedthrough) from the switches. The origins of these imperfections and techniques to minimise their effect are discussed.
D. Macquigg, T. Somerville
exaly +4 more sources
Reduction of operational amplifiers finite gain effects in switched-capacitor biquads [PDF]
Serbian Journal of Electrical Engineering, 2005 A combined approach for reducing the errors in the pole frequency f p, the pole Q - factor Qp and the magnitude at the pole frequency Hp, of switched capacitor biquads is presented.
Radev Nikolay, Ivanov Kantcho
doaj +3 more sources
A Sub-30 mpH Resolution Thin Film Transistor-Based Nanoribbon Biosensing Platform [PDF]
Sensors, 2017 We present a complete biosensing system that comprises a Thin Film Transistor (TFT)-based nanoribbon biosensor and a low noise, high-performance bioinstrumentation platform, capable of detecting sub-30 mpH unit changes, validated by an enzymatic ...
Ioannis Zeimpekis +6 more
doaj +2 more sources
Novel dynamic c.m.o.s. amplifier for switched-capacitor integrators
Electronics Letters, 1979 A novel dynamic c.m.o.s. amplifier for switched-capacitor integrators is described. The amplifier does not consume any static power and requires a very small chip area.
B. Hosticka
semanticscholar +2 more sources
Noise optimization of switched capacitor integrator
2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2015 The paper presents a method of noise optimization for a type of classical switched-capacitor(SC) integrators to design the distribution plan of capacitors in a specific layout area. The OP utilized in the SC integrator is a two-stage OP.
Xiao Wang, Zelin Shi, Baoshu Xu
semanticscholar +2 more sources
Offset and clock-feedthrough compensated switched-capacitor integrators
Electronics Letters, 1985 Switched-capacitor integrator circuits are described, in which the effects of amplifier offset and clock feedthrough are both compensated for using a sampled-data feedback path. Preliminary experimental results, obtained on circuits fabricated using a low-voltage CMOS technology, indicate 40?60 dB reduction in these effects.
J. Robert +4 more
semanticscholar +2 more sources
Switched-capacitor integrators with low finite-gain sensitivity
Electronics Letters, 1985 Compensated SC integrator stages are analysed and compared with respect to their sensitivities to finite amplifier gain effects. Simple single-stage amplifiers may be used in such circuits even in highly selective filtering applications. This may allow an extension of the present frequency range of SC circuits.
K. Haug, F. Maloberti, G. Temes
semanticscholar +3 more sources
Bottom-plate stray-insensitive bilinear switched-capacitor integrators
Electronics Letters, 1980 Switched-capacitor bilinear integrators are introduced which enable the exact design of leapfrog filters. The resulting networks are completely insensitive to the stray capacitances of the bottom plates.
D. C. V. Gruningen +2 more
semanticscholar +2 more sources
Design of Switched Capacitor Integrators using 90nm Technology
CVR Journal of Science & Technology, 2014 R. Ganesh
semanticscholar +3 more sources
Comparative analysis of two gain-and offset-compensated four-phase switched-capacitor integrators based on the second-order Adams-Bashworth’s integration method [PDF]
Serbian Journal of Electrical Engineering, 2004 Gain-and offset-compensated (GOC) modifications of four-phase inverting and no inverting switched-capacitor integrators based on the second-order Adams-Bashworth’s integration method are presented.
Radev Nikolay, Ivanov Kantcho
doaj +1 more source