Results 221 to 230 of about 189,977 (232)
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Gain- and offset-compensated switched-capacitor filters
1991 IEEE International Symposium on Circuits and Systems (ISCAS), 1991Novel gain- and offset-compensated (GOC) switched-capacitor bilinear and biquadratic sections using a two-phase clock are presented. Theoretical analysis and simulation results show that the frequency responses of these circuits have very low sensitivity to the finite operational amplifier (op-amp) gain, while the time responses are insensitive to ...
W.H. Ki, G.C. Temes
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Area-efficient gain- and offset-compensated very-large-time-constant SC biquads
[Proceedings] 1992 IEEE International Symposium on Circuits and Systems, 2003A signal flow graph analysis of K. Nagaraj's (1989) very large time-constant biquads based on charge splitting is described. With the addition of offset-storing capacitors, gain- and offset-compensated biquads are obtained. By applying the charge differencing technique, the biquads can be made very area efficient.
W.-H. Ki, G.C. Temes
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On-Focal Plane Analog-To-Digital Conversion With Detector Gain And Offset Compensation
SPIE Proceedings, 1989Hardware fabrication has been initiated on a test IC which has 32 channels of amplifiers, low pass anti-aliasing filters, 13-bit analog-to-digital (ND) converters per channel and a digital multiplexer. The single slope class of ND conversion is described, as are the unique variations required for incorporation on-focal plane.
David E. Ludwig +2 more
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IEEE Journal of Solid-State Circuits, 2002
A combination of continuous-time and switched capacitor integrators in a simulated LC lossless ladder yields a response with suppressed aliasing without the use of continuous-time prefiltering. Fabricated in a 0.35-/spl mu/m CMOS process, a fifth-order Cauer low-pass filter for a W-CDMA cellular phone receiver has a cutoff frequency of 1.92 MHz and ...
S. Azuma +4 more
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A combination of continuous-time and switched capacitor integrators in a simulated LC lossless ladder yields a response with suppressed aliasing without the use of continuous-time prefiltering. Fabricated in a 0.35-/spl mu/m CMOS process, a fifth-order Cauer low-pass filter for a W-CDMA cellular phone receiver has a cutoff frequency of 1.92 MHz and ...
S. Azuma +4 more
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ICM 2000. Proceedings of the 12th International Conference on Microelectronics. (IEEE Cat. No.00EX453), 2002
A novel gain- and offset-compensated (GOC) very large time constant (VLT) switched-capacitor (SC) integrator is presented and compared with the previously proposed Nagaraj-89 GOC VLT integrator in terms of gain error, phase error and offset voltage error. The effectiveness of the new integrator is demonstrated by designing a 60 Hz notch filter.
N.A. Radev, K.P. Ivanov
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A novel gain- and offset-compensated (GOC) very large time constant (VLT) switched-capacitor (SC) integrator is presented and compared with the previously proposed Nagaraj-89 GOC VLT integrator in terms of gain error, phase error and offset voltage error. The effectiveness of the new integrator is demonstrated by designing a 60 Hz notch filter.
N.A. Radev, K.P. Ivanov
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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360), 2003
This paper proposes an optimum design of a high frequency Switched-Capacitor IIR interpolation filter for Direct Digital Frequency Synthesizer systems. The circuit is formed by the combination of novel double sampling recursive direct-form II and non-recursive polyphase structures embedding mismatch-free analog delay lines with accurate, wideband gain-
null Seng-Pan U +3 more
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This paper proposes an optimum design of a high frequency Switched-Capacitor IIR interpolation filter for Direct Digital Frequency Synthesizer systems. The circuit is formed by the combination of novel double sampling recursive direct-form II and non-recursive polyphase structures embedding mismatch-free analog delay lines with accurate, wideband gain-
null Seng-Pan U +3 more
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2004
A gain- and offset- compensated switched-capacitor integrator based on the Simpson's integration method is presented Analytical expressions for the gain, phase and offset voltage errors are derived and compared with the corresponding errors of the earlier one uncompensated integrator.
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A gain- and offset- compensated switched-capacitor integrator based on the Simpson's integration method is presented Analytical expressions for the gain, phase and offset voltage errors are derived and compared with the corresponding errors of the earlier one uncompensated integrator.
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A 3.125Gb/s limit amplifier with 42dB gain and 1μs offset compensation in 0.18μm CMOS
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005., 2005E. Crain, M. Perrott
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2003
Two gain- and offset- compensated two-phase switched-;apacitor integrators based on the second-order Adams-Bashworth's ntegration method are presented. Analytical expressions for the gain, phase ind offset voltage errors are derived and compared with the corresponding errors of the earlier ones uncompensated integrators.
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Two gain- and offset- compensated two-phase switched-;apacitor integrators based on the second-order Adams-Bashworth's ntegration method are presented. Analytical expressions for the gain, phase ind offset voltage errors are derived and compared with the corresponding errors of the earlier ones uncompensated integrators.
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