Results 181 to 190 of about 107,683 (215)
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A 9000-gate user-programmable gate array
Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, 2003The 900-gate XC3090 CMOS user-programmable gate array is the largest member of a family of devices based on a second-generation logic cell array (LCA) architecture. This architecture features three types of user-configurable elements: an interior array of logic blocks, a perimeter of input/output (I/O) blocks, and interconnection resources ...
R. Kanazawa +7 more
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1988
Abstract : The authors propose a regular architecture, called recursive gate- arrays, suitable for circuits with modules of nonuniform size. A set of n (rectangular and L-shaped) modules can be placed in a recursive gate-array. The placement can be obtained in O(n log n) time. Keywords: VLSI layout placement, Knock-knee model.
Chiang, C., Maddila, S., Sarrafzadeh, M.
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Abstract : The authors propose a regular architecture, called recursive gate- arrays, suitable for circuits with modules of nonuniform size. A set of n (rectangular and L-shaped) modules can be placed in a recursive gate-array. The placement can be obtained in O(n log n) time. Keywords: VLSI layout placement, Knock-knee model.
Chiang, C., Maddila, S., Sarrafzadeh, M.
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Optically reconfigurable gate array
Proceedings 29th Applied Imagery Pattern Recognition Workshop, 2002Summary form only given, as follows. Reconfigurable processors, like the Field Programmable Gate Arrays (FPGAs), open new computational paradigms where the processor is able to tailor its internal structure to better implement a given application. A typical FPGA consists of an array of configurable logic blocks and a mesh of interconnections fully ...
Mumbru, J. +5 more
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An Overview of Bipolar Gate Arrays and a Report of an IIL Gate Array Design and Development
IETE Technical Review, 1990The paper discusses the trends of gate array development and gives a detailed overview of bipolar gate arrays developed over the past few years. A chronological survey of these gate arrays is presented in tabular form. The paper also includes an account of the design of an IIL gate array by the authors.
S Rakshit +4 more
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A 10K-Gate CMOS Gate Array Based on a Gate Isolation Structure
IEEE Journal of Solid-State Circuits, 1985This paper describes an effect of the "gate isolation" technique and its application to a 10K-gate CMOS gate-array VLSI chip. This gate array is fabricated using a 2-/spl mu/m n-well CMOS technology, with double-level metallization. As an example, a 32-bit parallel array multiplier is designed using a fully automatic CAD system.
T. Fujimura +5 more
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Microelectronics International, 1988 Software tools are an essential part of any IC design system but there are dangers associated with the introduction of CAD systems. This paper attempts to lift the software cloak which, along with the ubiquitous workstation, tends to cover the finer points of CMOS design.
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Microprocessors and Microsystems, 1988
Abstract The gate array approach to semicustom integrated circuit design is described. Traditional architectures are described, followed by some more recent introductions which attempt to eliminate some of the common limitations. Modern sea-of-gates architectures are shown to offer considerable potential.
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Abstract The gate array approach to semicustom integrated circuit design is described. Traditional architectures are described, followed by some more recent introductions which attempt to eliminate some of the common limitations. Modern sea-of-gates architectures are shown to offer considerable potential.
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1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1987
This paper will report on a gate array that employs Schottky diode capacitor-coupled logic to attain a noise margin of 400mV. At a power dissipation of 1mW%gate, the propagation delay was 284ps.
K. Kawakyu +8 more
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This paper will report on a gate array that employs Schottky diode capacitor-coupled logic to attain a noise margin of 400mV. At a power dissipation of 1mW%gate, the propagation delay was 284ps.
K. Kawakyu +8 more
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Hardware acceleration of gate array layout
Proceedings of the 22nd ACM/IEEE conference on Design automation - DAC '85, 1985In this paper we describe the hardware and software of a system which we have implemented to accelerate the physical design of gate arrays. In contrast to nearly all other reported approaches, our approach to hardware acceleration is to augment a single-user host workstation with a general-purpose microprogrammable slave processor having a large ...
Philip M. Spira, Carl Hage
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Proceedings 1988 IEEE International Conference on Computer Design: VLSI, 2003
It is noted that gate arrays have come of age in the 1980s and CMOS is the dominant technology. Major advances in manufacturing, architecture, and integrated CAD (computer-aided design) tools have allowed predictable delivery of circuits with 100000 used gates.
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It is noted that gate arrays have come of age in the 1980s and CMOS is the dominant technology. Major advances in manufacturing, architecture, and integrated CAD (computer-aided design) tools have allowed predictable delivery of circuits with 100000 used gates.
openaire +2 more sources