Results 191 to 200 of about 107,683 (215)
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ChemInform Abstract: Molecular Logic Gate Arrays
ChemInform, 2011AbstractReview: [167 refs.]
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Routing Techniques for Gate Array
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983This paper describes the routing techniques used for a Hughes internally developed high-density silicon-gate bulk CMOS gate array family. This layout software can be easily adapted to different array sizes and/or technologies (e.g., bipolar) through a change of parameters.
Bou Nin Tien, B.S. Ting
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Programmable Quantum Gate Arrays
Fortschritte der Physik, 2001We present a probabilistic quantum processor for qubits. The processor itself is represented by a fixed array of gates. The input of the processor is constituted by two registers. In the program register the set of instructions (program) is encoded. This program is applied to the data register.
Mark Hillery +2 more
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2nd International Conference on ASIC, 2002
BiCMOS gate array circuits and macrocell libraries are designed and fabricated through 2.0 /spl mu/m BiCMOS standard processes. The average gate delay time is as follows: BiCMOS 21 stage inverter, 1.1 ns; BiCMOS 21 stage oscillator, 1.1 ns; BiCMOS 21 stage NAND, 1.3 ns; BiCMOS 21 stage NOR, 1.4 ns.
Min Zhang, Xuhong Hu, Meiyuan Wang
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BiCMOS gate array circuits and macrocell libraries are designed and fabricated through 2.0 /spl mu/m BiCMOS standard processes. The average gate delay time is as follows: BiCMOS 21 stage inverter, 1.1 ns; BiCMOS 21 stage oscillator, 1.1 ns; BiCMOS 21 stage NAND, 1.3 ns; BiCMOS 21 stage NOR, 1.4 ns.
Min Zhang, Xuhong Hu, Meiyuan Wang
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Microelectronic Engineering, 2001
Abstract The successful fabrication of field emission (FE) devices is directly related to process simplicity and device performance, which depends to a large extent on the tip material and emitter geometry. On the other hand, these characteristics are the most important issues influencing industrial applicability of the FE devices.
Tomasz Debski +11 more
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Abstract The successful fabrication of field emission (FE) devices is directly related to process simplicity and device performance, which depends to a large extent on the tip material and emitter geometry. On the other hand, these characteristics are the most important issues influencing industrial applicability of the FE devices.
Tomasz Debski +11 more
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IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1982
Because of the increasing complexity of new integrated circuits (IC's) and the limited supply of IC designers, structured design approaches are necessary. A gate array is a common approach to structuring, formalizing, and thus simplifying the design process.
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Because of the increasing complexity of new integrated circuits (IC's) and the limited supply of IC designers, structured design approaches are necessary. A gate array is a common approach to structuring, formalizing, and thus simplifying the design process.
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984
We propose a new approach to the global routing of gate arrays. The method can handle any channel capacities and pin distributions on the chip. The global router first finds unique routes, then pushes connections to the periphery. As outer wiring capacity is consumed, the routing continues inward, connecting pins and making global cell assignments for ...
Malgorzata Marek-Sadowska, Jeong-Tyng Li
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We propose a new approach to the global routing of gate arrays. The method can handle any channel capacities and pin distributions on the chip. The global router first finds unique routes, then pushes connections to the periphery. As outer wiring capacity is consumed, the routing continues inward, connecting pins and making global cell assignments for ...
Malgorzata Marek-Sadowska, Jeong-Tyng Li
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Inkjet-Configurable Gate Array
2018Over the last decades, Organic Electronics has been emerging as a multidisciplinary and innovative way to generate electronic devices and systems. It is intended to provide a platform for low-cost, large-area, and low-frequency Printable Electronics on a variety of substrates, including flexible plastic substrates.
Lluis Teres +2 more
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IEEE Journal of Solid-State Circuits, 1980
The dimensions of the fundamental gate cell were analyzed in the gate-array type masterslice LSI which utilized the DSA MOS process combined with two-level metallization technology. It was revealed that the optimum gate width was 80 µm in the 4-µm design rule, taking the total power dissipation of 3 W and the delay time below 2 ns into consideration ...
I. Ohkura +3 more
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The dimensions of the fundamental gate cell were analyzed in the gate-array type masterslice LSI which utilized the DSA MOS process combined with two-level metallization technology. It was revealed that the optimum gate width was 80 µm in the 4-µm design rule, taking the total power dissipation of 3 W and the delay time below 2 ns into consideration ...
I. Ohkura +3 more
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Trends in gate array technology
Microelectronics Journal, 1983This paper takes a look at where the IC industry is headed today in the evolution of gate array technology. Projections are made of advancements in gate array technology including both array architecture and design methodology. Historically, the concept of a gate array is at least 15 years old.
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