Results 311 to 320 of about 2,178,356 (388)
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Superconducting Magnetic Field Programmable Gate Array
IEEE transactions on applied superconductivity, 2018Field-programmable gate arrays (FPGAs) provide a significantly cheaper solution for various applications in traditional semiconductor electronics. Single flux quantum (SFQ) technologies are developing rapidly and the availability of SFQ-specific FPGA ...
N. Katam, O. Mukhanov, Massoud Pedram
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Programmable Quantum Gate Arrays
Fortschritte der Physik, 2001Summary: We present a probabilistic quantum processor for qubits. The processor itself is represented by a fixed array of gates. The input of the processor is constituted by two registers. In the program register the set of instructions (program) is encoded. This program is applied to the data register.
Mark Hillery +2 more
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1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1982
This paper will describe a gate array with a loaded propagation delay of 2ns per gate. The device employs 2μm rules, double metal layers, silicon gate technology and bent-gate patterns for a minimum chip area.
M. Asano +8 more
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This paper will describe a gate array with a loaded propagation delay of 2ns per gate. The device employs 2μm rules, double metal layers, silicon gate technology and bent-gate patterns for a minimum chip area.
M. Asano +8 more
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IEEE Journal of Solid-State Circuits, 1984
A method for converting integrated circuit personalizations from a technology providing one set of design rules to a technology with a different and smaller set of design rules is presented. An example showing a conversion to a new technology where the cell area was reduced by 59% and the speed was increased more than 4.0% is illustrated.
K.J. Reasoner, D.W. Still, L.A. Akers
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A method for converting integrated circuit personalizations from a technology providing one set of design rules to a technology with a different and smaller set of design rules is presented. An example showing a conversion to a new technology where the cell area was reduced by 59% and the speed was increased more than 4.0% is illustrated.
K.J. Reasoner, D.W. Still, L.A. Akers
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A 9000-gate user-programmable gate array
Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, 2003The 900-gate XC3090 CMOS user-programmable gate array is the largest member of a family of devices based on a second-generation logic cell array (LCA) architecture. This architecture features three types of user-configurable elements: an interior array of logic blocks, a perimeter of input/output (I/O) blocks, and interconnection resources ...
R. Kanazawa +7 more
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Active pixel sensor matrix based on monolayer MoS2 phototransistor array
Nature Materials, 2022Akhil Dodda +2 more
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1988
Abstract : The authors propose a regular architecture, called recursive gate- arrays, suitable for circuits with modules of nonuniform size. A set of n (rectangular and L-shaped) modules can be placed in a recursive gate-array. The placement can be obtained in O(n log n) time. Keywords: VLSI layout placement, Knock-knee model.
Chiang, C., Maddila, S., Sarrafzadeh, M.
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Abstract : The authors propose a regular architecture, called recursive gate- arrays, suitable for circuits with modules of nonuniform size. A set of n (rectangular and L-shaped) modules can be placed in a recursive gate-array. The placement can be obtained in O(n log n) time. Keywords: VLSI layout placement, Knock-knee model.
Chiang, C., Maddila, S., Sarrafzadeh, M.
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An Overview of Bipolar Gate Arrays and a Report of an IIL Gate Array Design and Development
IETE Technical Review, 1990The paper discusses the trends of gate array development and gives a detailed overview of bipolar gate arrays developed over the past few years. A chronological survey of these gate arrays is presented in tabular form. The paper also includes an account of the design of an IIL gate array by the authors.
S Rakshit +4 more
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A 10K-Gate CMOS Gate Array Based on a Gate Isolation Structure
IEEE Journal of Solid-State Circuits, 1985This paper describes an effect of the "gate isolation" technique and its application to a 10K-gate CMOS gate-array VLSI chip. This gate array is fabricated using a 2-/spl mu/m n-well CMOS technology, with double-level metallization. As an example, a 32-bit parallel array multiplier is designed using a fully automatic CAD system.
T. Fujimura +5 more
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Microprocessors and Microsystems, 1988
Abstract The gate array approach to semicustom integrated circuit design is described. Traditional architectures are described, followed by some more recent introductions which attempt to eliminate some of the common limitations. Modern sea-of-gates architectures are shown to offer considerable potential.
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Abstract The gate array approach to semicustom integrated circuit design is described. Traditional architectures are described, followed by some more recent introductions which attempt to eliminate some of the common limitations. Modern sea-of-gates architectures are shown to offer considerable potential.
openaire +2 more sources