Results 81 to 90 of about 2,139,815 (232)
Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET
Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS
Gao Y.+11 more
core +1 more source
An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic [PDF]
In this paper, an efficient implementation of a 16 bit array hierarchy multiplier using full swing Gate Diffusion Input (GDI) logic is discussed. Hierarchy multiplier is attractive because of its ability to carry the multiplication operation within one ...
Shoba Mohan, Nakkeeran Rangaswamy
doaj +1 more source
Impact of Parallel Gating on Gate Fidelities in Linear, Square, and Star Arrays of Noisy Flip-Flop Qubits [PDF]
Successfully implementing a quantum algorithm involves maintaining a low logical error rate by ensuring the validity of the quantum fault-tolerance theorem. The required number of physical qubits arranged in an array depends on the chosen Quantum Error Correction code and the achievable physical qubit error rate.
arxiv +1 more source
Tunneling Qubit Operation on a Protected Josephson Junction Array
We discuss a protected quantum computation process based on a hexagon Josephson junction array. Qubits are encoded in the punctured array, which is topologically protected. The degeneracy is related to the number of holes.
J. Preskill+5 more
core +1 more source
This paper develops a primitive gas recognition system for discriminating between industrial gas species. The system under investigation consists of an array of eight micro-hotplate-based SnO2 thin film gas sensors with different selectivity patterns ...
F. Benrekia, M. Attari, M. Bouhedda
semanticscholar +1 more source
The Gate Array Implementation of an Area Calculation Pipeline [PDF]
A gate array is a semi-custom designed integrated circuit. The integrated circuit is designed by a customer and then turned over to a vendor to be manufactured.
Janssen, Edward J.
core +1 more source
Collapse of superconductivity in a hybrid tin-graphene Josephson junction array
When a Josephson junction array is built with hybrid superconductor/metal/superconductor junctions, a quantum phase transition from a superconducting to a two-dimensional (2D) metallic ground state is predicted to happen upon increasing the junction ...
A Allain+49 more
core +3 more sources
CORRIGENDUM A hybrid swarm intelligence of artificial immune system tuned with Taguchi–genetic algorithm and its field-programmable gate array realization to optimal inverse kinematics for an articulated industrial robotic manipulator Owing to errors ...
doaj +1 more source
Automatic Qubit Characterization and Gate Optimization with QubiC [PDF]
As the size and complexity of a quantum computer increases, quantum bit (qubit) characterization and gate optimization become complex and time-consuming tasks. Current calibration techniques require complicated and verbose measurements to tune up qubits and gates, which cannot easily expand to the large-scale quantum systems.
arxiv
Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System
A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas.
Jong-Ryul Yang+2 more
doaj +1 more source