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GPU-Ether: GPU-native Packet I/O for GPU Applications on Commodity Ethernet
IEEE INFOCOM 2021 - IEEE Conference on Computer Communications, 2021Despite the advent of various network enhancement technologies, it is yet a challenge to provide high-performance networking for GPU-accelerated applications on commodity Ethernet. Kernel-bypass I/O, such as DPDK or netmap, which is normally optimized for host memory-based CPU applications, has limitations on improving the performance of GPU ...
Changue Jung +4 more
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Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems, 2013
Us have evolved to programmable, energy efficient compute accelerators for massively parallel applications. Still, compute power is lost in many applications because of cycles spent on data movement and control instead of computations on actual data. Additional cycles can be lost as well on pipeline stalls due to long latency operations.
Braak, van den, G.J.W., Corporaal, H.
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Us have evolved to programmable, energy efficient compute accelerators for massively parallel applications. Still, compute power is lost in many applications because of cycles spent on data movement and control instead of computations on actual data. Additional cycles can be lost as well on pipeline stalls due to long latency operations.
Braak, van den, G.J.W., Corporaal, H.
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2006
Points, lines, and polygons have been the fundamental primitives in graphics. Graphics hardware is optimized to handle them in a pipeline. Other objects are converted to these primitives before rendering. Programmable GPUs have made it possible to introduce a wide class of computations on each vertex and on each fragment.
Sunil Mohan Ranta +2 more
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Points, lines, and polygons have been the fundamental primitives in graphics. Graphics hardware is optimized to handle them in a pipeline. Other objects are converted to these primitives before rendering. Programmable GPUs have made it possible to introduce a wide class of computations on each vertex and on each fragment.
Sunil Mohan Ranta +2 more
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Proceedings of the ACM International Conference on Supercomputing, 2019
Future High-Performance Computing (HPC) systems will likely be composed of accelerator-dense heterogeneous computers because accelerators are able to deliver higher performance at lower costs, socket counts and energy consumption. Such accelerator-dense nodes pose a reliability challenge because preserving a large amount of state within accelerators ...
Kyushick Lee +5 more
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Future High-Performance Computing (HPC) systems will likely be composed of accelerator-dense heterogeneous computers because accelerators are able to deliver higher performance at lower costs, socket counts and energy consumption. Such accelerator-dense nodes pose a reliability challenge because preserving a large amount of state within accelerators ...
Kyushick Lee +5 more
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ACM SIGGRAPH 2008 classes, 2008
A gamer wanders through a virtual world rendered in nearcinematic detail. Seconds later, the screen fills with a 3D explosion, the result of unseen enemies hiding in physically accurate shadows. Disappointed, the user exits the game and returns to a computer desktop that exhibits the stylish 3D look-and-feel of a modern window manager.
Kayvon Fatahalian, Mike Houston
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A gamer wanders through a virtual world rendered in nearcinematic detail. Seconds later, the screen fills with a 3D explosion, the result of unseen enemies hiding in physically accurate shadows. Disappointed, the user exits the game and returns to a computer desktop that exhibits the stylish 3D look-and-feel of a modern window manager.
Kayvon Fatahalian, Mike Houston
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Proceedings of the 26th ACM international conference on Supercomputing, 2012
Graphics Processing Units (GPUs) have become ideal candidates for the development of fine-grain parallel algorithms as the number of processing elements per GPU increases. In addition to the increase in cores per system, new memory hierarchies and increased bandwidth have been developed that allow for significant performance improvement when ...
Oded Green +2 more
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Graphics Processing Units (GPUs) have become ideal candidates for the development of fine-grain parallel algorithms as the number of processing elements per GPU increases. In addition to the increase in cores per system, new memory hierarchies and increased bandwidth have been developed that allow for significant performance improvement when ...
Oded Green +2 more
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ScaleGPU: GPU Architecture for Memory-Unaware GPU Programming
IEEE Computer Architecture Letters, 2014Programmer-managed GPU memory is a major challenge in writing GPU applications. Programmers must rewrite and optimize an existing code for a different GPU memory size for both portability and performance. Alternatively, they can achieve only portability by disabling GPU memory at the cost of significant performance degradation.
Youngsok Kim +3 more
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GPU-S2S: A Compiler for Source-to-Source Translation on GPU
2010 3rd International Symposium on Parallel Architectures, Algorithms and Programming, 2010CUDA facilitates the development of General Purpose computing on Graphics Processing Units (GPGPU), however, its complex memory system, thread-level structure, and data transmission control between memories have brought great challenges for programming on GPU.
Dan Li +3 more
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Topology-Aware GPU Selection on Multi-GPU Nodes
2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2016GPU accelerators have successfully established themselves in modern HPC clusters due to their high performance and energy efficiency. To increase the GPU computational power in a cluster node and tackle larger problems, multi-GPU nodes have become the platform of choice for scientific applications.
Iman Faraji +2 more
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