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2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2023
sponsorship: This work was supported in part by CyberSecurity Research Flanders with reference number VR20192203, the Horizon 2020 ERC Advanced Grant (101020005 Belfort) and by Darpa DPRIVE (Contract No. HR0011-21-C-0034). Michiel Van Beirendonck is funded by FWO PhD fellow (1SD5621N).
Bertels, Jonas +3 more
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sponsorship: This work was supported in part by CyberSecurity Research Flanders with reference number VR20192203, the Horizon 2020 ERC Advanced Grant (101020005 Belfort) and by Darpa DPRIVE (Contract No. HR0011-21-C-0034). Michiel Van Beirendonck is funded by FWO PhD fellow (1SD5621N).
Bertels, Jonas +3 more
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IEEE Micro, 2018 Hardware Accelerated Voxelisation
Computers & Graphics, 2000Abstract This paper presents a hardware accelerated approach to the voxelization of a wide range of 3D objects, including curves/surfaces, solids, and volumetric CSG models. It allows 3D scenes to be modeled and manipulated in their own representations, and generates the volume representations of regions of interest on-the-fly for volumetric ...
Shiaofen Fang, Hongsheng Chen
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Hardware Accelerator for BLAST
2012 IEEE 6th International Symposium on Embedded Multicore SoCs, 2012The basic local alignment search tool (BLAST) is one of the most popular sequence alignment tools available. Sequence alignment is used to extract similar parts of an input protein (or DNA) sequence from protein (or DNA) databases, in order to investigate biological evolution and genomic genealogy.
Shizuka Ishikawa +2 more
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Hardware Accelerated Data Analysis
Parallel Computing in Electrical Engineering, International Conference on, 2004In this paper we present a massively parallel hardware accelerator for neural network based data mining applications. We use Self-Organizing Maps (SOM) for the analysis of very large datasets. One example is the analysis of semiconductor fabrication process data, which demands very high performance in order to achieve acceptable simulation times.
Franzmeier, M. +4 more
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Multimedia Execution Hardware Accelerator
Journal of VLSI signal processing systems for signal, image and video technology, 2001zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Edwin A. Hakkennes, Stamatis Vassiliadis
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Hardware Accelerator for Prediction of Exons
2006 International Conference of the IEEE Engineering in Medicine and Biology Society, 2006Gene annotation is by nature a computationally intensive problem, as it needs to process huge data size of DNA sequences. This forces the need to look for alternate ways of implementing algorithms to predict exons. The paper presents an accelerator for indexing DNA sequences.
Adeel Yusuf, Shoab A. Khan
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Proceedings of the 2017 ACM International Conference on Management of Data, 2017
Relational databases provide a wealth of functionality to a wide range of applications. Yet, there are tasks for which they are less than optimal, for instance when processing becomes more complex (e.g., regular expression evaluation, data analytics) or the data is less structured (e.g., text or long strings).
David Sidler +4 more
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Relational databases provide a wealth of functionality to a wide range of applications. Yet, there are tasks for which they are less than optimal, for instance when processing becomes more complex (e.g., regular expression evaluation, data analytics) or the data is less structured (e.g., text or long strings).
David Sidler +4 more
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A-QED Verification of Hardware Accelerators
2020 57th ACM/IEEE Design Automation Conference (DAC), 2020We present A-QED (Accelerator-Quick Error Detection), a new approach for pre-silicon formal verification of stand-alone hardware accelerators. A-QED relies on bounded model checking -- however, it does not require extensive design-specific properties or a full formal design specification. While A- QED is effective for both RTL and high-level synthesis (
Eshan Singh +12 more
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