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Proceedings of the 2017 ACM International Conference on Management of Data, 2017
Relational databases provide a wealth of functionality to a wide range of applications. Yet, there are tasks for which they are less than optimal, for instance when processing becomes more complex (e.g., regular expression evaluation, data analytics) or the data is less structured (e.g., text or long strings).
David Sidler +4 more
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Relational databases provide a wealth of functionality to a wide range of applications. Yet, there are tasks for which they are less than optimal, for instance when processing becomes more complex (e.g., regular expression evaluation, data analytics) or the data is less structured (e.g., text or long strings).
David Sidler +4 more
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A-QED Verification of Hardware Accelerators
2020 57th ACM/IEEE Design Automation Conference (DAC), 2020We present A-QED (Accelerator-Quick Error Detection), a new approach for pre-silicon formal verification of stand-alone hardware accelerators. A-QED relies on bounded model checking -- however, it does not require extensive design-specific properties or a full formal design specification. While A- QED is effective for both RTL and high-level synthesis (
Eshan Singh +12 more
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A hardware accelerator for maze routing
24th ACM/IEEE conference proceedings on Design automation conference - DAC '87, 1987A hardware accelerator for the maze routing problem is developed. This accelerator consists of three three-stage pipelines. Banked memory is used to avoid memory read/write conflicts and obtain maximum efficiency. The design is compared to other proposed designs. Unlike other proposed hardware solutions for this problem, this design does not require an
Youngju Won +2 more
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Hardware acceleration for Window systems
Proceedings of the 16th annual conference on Computer graphics and interactive techniques, 1989Graphics pipelines are quickly evolving to support multitasking workstations. The driving force behind this evolution is the window system, which must provide high performance graphics within multiple windows, while maintaining interactivity. The virtual graphics system presented by [7] provides a clean solution to the problem of context switching ...
Desi Rhoden, Chris Wilcox
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Hardware acceleration of Scatter Search
2010 International Conference on High Performance Computing & Simulation, 2010In this paper, we share our experience implementing the well-known meta-heuristic, Scatter Search, on a Field-Programmable Gate-Array (FPGA). Our objective is to improve the runtime of scatter search by exploiting the potential performance benefits that are available through the native parallelism in hardware. When implementing scatter search we employ
Maxwell Walton +2 more
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Hardware acceleration of Hadoop MapReduce
2013 IEEE International Conference on Big Data, 2013MapReduce is widely used for BigData processing. It was originally designed to overcome the I/O bottleneck of commodity servers. However, several high speed storage and network devices have recently emerged, and speeds continue to increase. Employing such brand new devices will solve the I/O bottleneck, making the CPU the next serious bottleneck in the
Toshimori Honjo, Kazuki Oikawa
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Hardware Acceleration of Searchable Encryption
Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, 2018Searchable symmetric encryption (SSE) allows a client to outsource the storage of her data to an (untrusted) server in a private manner, while maintaining the ability to selectively search over it. A key feature of all existing SSE schemes is the tradeoff between security (in terms of the information leakage to the server) and efficiency (in terms of ...
Arnab Bag +3 more
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Hardware Acceleration for Machine Learning
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017This paper presents an approach to enhance the performance of machine learning applications based on hardware acceleration. This approach is based on parameterised architectures designed for Convolutional Neural Network (CNN) and Support Vector Machine (SVM), and the associated design flow common to both.
Ruizhe Zhao +4 more
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A hardware cache memcpy accelerator
2006 IEEE International Conference on Field Programmable Technology, 2006In this paper, we present a hardware solution to perform the commonly used memcpy operation with the goal to reduce the time to perform the actual memory copies. This is accomplished by taking advantage of the presence of a cache that is found next to many current-day (embedded) processors. Additionally, the currently presented solution assumes that to
Stephan Wong +2 more
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