Results 21 to 30 of about 25,587 (261)

Hardware Acceleration of Number Theoretic Transform in zk-SNARK [PDF]

Jisuanji kexue yu tansuo
The proof in zk-SNARK has a fixed length and can be verified quickly, promoting the application of zero-knowledge proof in areas such as digital signature, blockchain, distributed storage, and outsourced computing.
ZHAO Haixu, CHAI Zhilei, HUA Pengcheng, WANG Feng, DING Dong
doaj   +1 more source

Hardware-Accelerated Simulated Radiography [PDF]

VIS 05. IEEE Visualization, 2005., 2006
We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32-bit floating point texture capabilities to obtain solutions to the radiative ...
Daniel E. Laney, Steven P. Callahan, Nelson L. Max, Cláudio T. Silva, Steven Langer, Randall Frank   +5 more
openaire   +1 more source

Custom Hardware Inference Accelerator for TensorFlow Lite for Microcontrollers

IEEE Access, 2022
In recent years, the need for the efficient deployment of Neural Networks (NN) on edge devices has been steadily increasing. However, the high computational demand required for Machine Learning (ML) inference on tiny microcontroller-based IoT devices ...
Erez Manor, Shlomo Greenberg
doaj   +1 more source

Orchestration mechanism for VNF hardware acceleration resources in SDN/NFV architecture

Tongxin xuebao, 2018
The hardware acceleration mechanism for VNF (virtual network function) is recently a hot research topic in SDN/NFV architecture because of the low processing performance of VNF.Once hardware acceleration resources have been plugged into the network,how ...
Tong DUAN, Julong LAN, Yuxiang HU, Hongwei FAN   +3 more
doaj   +2 more sources

Real-time acceleration design of Canny algorithm based on Vivado HLS

Dianzi Jishu Yingyong, 2018
On the shortcomings of Canny edge detection algorithm in the real-time image processing time-consuming and large amount of data for computation, the hardware acceleration method of Canny edge detection algorithm using Vivado HLS is proposed.
Tan Jiancheng, Wu Dingxiang, Li Mingxin, Tang Lijun   +3 more
doaj   +1 more source

Code Transpilation for Hardware Accelerators

CoRR, 2023
DSLs and hardware accelerators have proven to be very effective in optimizing computationally expensive workloads. In this paper, we propose a solution to the challenge of manually rewriting legacy or unoptimized code in domain-specific languages and hardware accelerators. We introduce an approach that integrates two open-source tools: Metalift, a code
Yuto Nishida, Sahil Bhatia, Shadaj Laddad, Hasan Genc, Yakun Sophia Shao, Alvin Cheung   +5 more
openaire   +2 more sources

Hardware Acceleration of Neural Graphics

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Rendering and inverse-rendering algorithms that drive conventional computer graphics have recently been superseded by neural representations (NR). NRs have recently been used to learn the geometric and the material properties of the scenes and use the information to synthesize photorealistic imagery, thereby promising a replacement for traditional ...
Muhammad Husnain Mubarik, Ramakrishna Kanungo, Tobias Zirr, Rakesh Kumar 0002   +3 more
openaire   +2 more sources

Acceleration of LSTM With Structured Pruning Method on FPGA

IEEE Access, 2019
This paper focuses on accelerating long short-term memory (LSTM), which is one of the popular types of recurrent neural networks (RNNs). Because of the large number of weight memory accesses and high computation complexity with the cascade-dependent ...
Shaorun Wang, Peng Lin, Ruihan Hu, Hao Wang, Jin He, Qijun Huang, Sheng Chang   +6 more
doaj   +1 more source

A Low-Power Hardware Architecture for Real-Time CNN Computing

Sensors, 2023
Convolutional neural network (CNN) is widely deployed on edge devices, performing tasks such as objective detection, image recognition and acoustic recognition.
Xinyu Liu, Chenhong Cao, Shengyu Duan
doaj   +1 more source

Hardware Accelerated Power Estimation [PDF]

Design, Automation and Test in Europe, 2005
In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the observation that the functions necessary for power estimation (power model evaluation, aggregation, etc.) can be implemented as hardware circuits.
Joel Coburn, Srivaths Ravi 0001, Anand Raghunathan   +2 more
openaire   +3 more sources