Results 31 to 40 of about 193,534 (289)
Orchestration mechanism for VNF hardware acceleration resources in SDN/NFV architecture
Tongxin xuebao, 2018 The hardware acceleration mechanism for VNF (virtual network function) is recently a hot research topic in SDN/NFV architecture because of the low processing performance of VNF.Once hardware acceleration resources have been plugged into the network,how ...
Tong DUAN +3 more
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Real-time acceleration design of Canny algorithm based on Vivado HLS
Dianzi Jishu Yingyong, 2018 On the shortcomings of Canny edge detection algorithm in the real-time image processing time-consuming and large amount of data for computation, the hardware acceleration method of Canny edge detection algorithm using Vivado HLS is proposed.
Tan Jiancheng +3 more
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A survey of real-time crowd rendering [PDF]
, 2016 In this survey we review, classify and compare existing approaches for real-time crowd rendering. We first overview character animation techniques, as they are highly tied to crowd rendering performance, and then we analyze the state of the art in crowd ...
Andújar Gran, Carlos Antonio +2 more
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Resistive Neural Hardware Accelerators
Proceedings of the IEEE, 2023 Deep Neural Networks (DNNs), as a subset of Machine Learning (ML) techniques, entail that real-world data can be learned and that decisions can be made in real-time. However, their wide adoption is hindered by a number of software and hardware limitations. The existing general-purpose hardware platforms used to accelerate DNNs are facing new challenges
Kamilya Smagulova +4 more
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Acceleration of LSTM With Structured Pruning Method on FPGA
IEEE Access, 2019 This paper focuses on accelerating long short-term memory (LSTM), which is one of the popular types of recurrent neural networks (RNNs). Because of the large number of weight memory accesses and high computation complexity with the cascade-dependent ...
Shaorun Wang +6 more
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Biomolecular electrostatics using a fast multipole BEM on up to 512 GPUs and a billion unknowns
, 2011 We present teraflop-scale calculations of biomolecular electrostatics enabled by the combination of algorithmic and hardware acceleration. The algorithmic acceleration is achieved with the fast multipole method (FMM) in conjunction with a boundary ...
Barba, L. A. +4 more
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The use of field-programmable gate arrays for the hardware acceleration of design automation tasks [PDF]
, 1996 This paper investigates the possibility of using Field-Programmable Gate Arrays (Fr’GAS) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design ...
Allinson, Nigel M. +2 more
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Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration
, 2017 State-of-the-art convolutional neural networks are enormously costly in both compute and memory, demanding massively parallel GPUs for execution. Such networks strain the computational capabilities and energy available to embedded and mobile processing ...
Gupta, Rajesh K. +6 more
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UniFL: Accelerating Federated Learning Using Heterogeneous Hardware Under a Unified Framework
IEEE AccessFederated learning (FL) is now considered a critical method for breaking down data silos. However, data encryption can significantly increase computing time, limiting its large-scale deployment.
Biyao Che +6 more
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Design of IGBT parameter prediction hardware system based on LSTM network
Dianzi Jishu Yingyong, 2019 Parameter prediction of insulated gate bipolar transistor(IGBT) can effectively avoid the economic loss and safety problem caused by its failure. Based on the analysis of IGBT parameters, the paper designs a SoC hardware system of IGBT parameters ...
Li Yuanbo, Yang Yuan, Zhang Xiaotao
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