Hardware Accelerators for Cardiovascular Signal Processing: A System-on-Chip Perspective. [PDF]
Hariri R +4 more
europepmc +1 more source
Spatial‐Wavelength Multiplexing Error‐Controlled Photonic Analog Computing System
A novel photonic integrated circuit prototype implementing the concept of general‐purpose analog computing and demonstrate its capability in radio frequency applications. The chip features a multichannel architecture and performs fully optical analog computation with frequency‐domain parallel processing. An FPGA‐based error‐correction algorithm aims to
Tao Zhu +15 more
wiley +1 more source
Inverse-designed nanophotonic neural network accelerators for ultra-compact optical computing. [PDF]
Sved J +5 more
europepmc +1 more source
This work introduces an open‐source all‐optical platform for functional phenotyping of human stem cell‐derived neurons. The system integrates optogenetics, calcium imaging, automated acquisition, and analysis to resolve single‐cell and network activity, enabling longitudinal measurements, disease modeling, and pharmacological screening in preclinical ...
Wardiya Afshar‐Saber +12 more
wiley +1 more source
Domain-Specific Acceleration of Gravity Forward Modeling via Hardware-Software Co-Design. [PDF]
Yang Y, Sun D, Ma Z, Gu W.
europepmc +1 more source
Artificial Neuron Based on Electrical Anisotropy from WSe2 Field Effect Transistors
An artificial neuron was realized based on the anisotropic mobility of WSe2. Dendritic and axon‐multisynaptic performance of a neuron was achieved with optical and voltage pulses. Recognition accuracy of handwritten digits was obtained to 97% based on the synaptic weight of an artificial neuron.
Qi Sun +10 more
wiley +1 more source
A Codesign Framework for the Development of Next Generation Wearable Computing Systems. [PDF]
Porreca F, Frustaci F, Gravina R.
europepmc +1 more source
Hardware-Accelerated neural network
This work presents a parametrizable design of a neural network on an FPGA, being trained previously in the CPU using backpropagation. We test different configurations and report delay, power and area.
openaire +1 more source
Tunable Switching Mechanisms in HfZrO2‐Based Tunnel Junctions for High‐Performance Synaptic Arrays
This work demonstrates hybrid switching in engineered HZO‐based FTJs, enabled by controlled interlayer design and oxygen scavenging dynamics. The combined switching mechanism produces robust multilevel conductance states in large crossbar arrays, offering a materials‐driven pathway toward scalable in‐memory computing with enhanced tunability and ...
Jiwon You +8 more
wiley +1 more source
Design and Implementation of a YOLOv2 Accelerator on a Zynq-7000 FPGA. [PDF]
Kim H, Kim TK.
europepmc +1 more source

