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Hardware architecture exploration: automatic exploration of distributed automotive hardware architectures

Software and Systems Modeling, 2020
As the engineering of distributed embedded systems is getting more and more complex, due to increasingly sophisticated functionalities demanding more and more powerful hardware, model-based development of software-intensive embedded systems has become a de facto standard in recent years.
Johannes Eder   +4 more
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EDS hardware architecture

1990
The consortium of Bull, ECRC, ICL, Siemens and their associates is currently designing a 256 Processing Element machine and, by 1992, will have built three prototypes; to date the definitive specification has been produced. This paper describes the hardware architecture and system support necessary for a distributed store architecture; in particular ...
Mike Ward   +2 more
openaire   +1 more source

A HARDWARE IMPLEMENTATION OF THE APE100 ARCHITECTURE

International Journal of Modern Physics C, 1993
APE100 processors are based on a simple Single Instruction Multiple Data architecture optimized for the simulation of Lattice Field Theories or other complex physical systems. This paper describes the hardware implementation of the first APE100 machine.
BARTOLONI A   +16 more
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Database Architectures for New Hardware

21st International Conference on Data Engineering (ICDE'05), 2004
Few years ago, DBMS stored data on disks and cached recently used data in main memory buffer pools, while designers worried about improving I/O performance and maximizing main memory utilization. Today, however, databases live in multi-level memory hierarchies that include disks, main memories, and several levels of processor caches.
openaire   +3 more sources

Reliable hardware-software architecture

Proceedings of the international conference on Reliable software -, 1975
This paper deals with the problem of reliability in a hardware/software system. More specifically it deals with the strategy used to achieve reliability in a particular hardware/software system built by the author and his colleagues at Carnegie-Mellon University.
openaire   +1 more source

A hardware architecture for subtractive clustering

International Journal of High Performance Systems Architecture, 2011
Clustering algorithms are used extensively to organise and categorise abundant data. This paper describes the implementation of subtractive clustering algorithm in hardware. The solution developed in this paper seeks a hardware implementation to automatic and fast identification of cluster centres. This hardware proposed is generic so it can be used in
Marcos Santana Farias   +2 more
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Architecture of a Hardware Data Interpreter

IEEE Transactions on Computers, 1977
DATA INTERPRETATION REFERS TO THE EXECUTION OF THE DATA DECLARATIONS OF A HIGH-LEVEL PROGRAMMING LANGUAGE PROGRAM, WHICH DECLARE THE DATA TYPES AND THE DATA STRUCTURES IN THE PROGRAM. THIS PAPER PRESENTS A DATA INTERPRETER WITH A HIGH-LEVEL MEMORY STRUCTURE WHERE THE DATA IS STORED IN A RANDOM-ACCESS MEMORY, WHILE THE TYPE, STRUCTURAL, AND REFERENCING ...
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The architecture for a hardware immune system

Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001, 2002
Since the advent of fault tolerance in the 1960s, numerous techniques have been developed to increase the reliability of safety critical and space borne missions. In the last decade novel approaches to this field have sought inspiration from nature in the form of evolutionary and developmental forms of fault tolerance.
Daryl W. Bradley, Andrew M. Tyrrell
openaire   +1 more source

Stochastic hardware architectures: A survey

2012 International Conference on Energy Aware Computing, 2012
Many emerging computer applications may be classified into recognition, mining, and synthesis (RMS) applications, or into stream-based media applications. One interesting and useful property of such applications is that they are tolerant to errors. In fact, these applications allow discrepancies in intermediate computations, but nevertheless are able ...
Sarah Abdallah   +3 more
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Verifying a hardware security architecture

Proceedings. 1990 IEEE Computer Society Symposium on Research in Security and Privacy, 1990
The verification work reported had three goals: (1) to develop a method for specifying components, which may be either software processes or hardware components, in terms of their possible event histories (also called traces); (2) to develop a method of verifying systems built from such components; and (3) to use these techniques to prove security ...
Joshua D. Guttman, H.-P. Ko
openaire   +1 more source

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