Results 211 to 220 of about 72,027 (265)
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A hardware architecture for surface splatting
ACM SIGGRAPH 2007 papers, 2007We present a novel architecture for hardware-accelerated rendering of point primitives. Our pipeline implements a refined version of EWA splatting, a high quality method for antialiased rendering of point sampled representations. A central feature of our design is the seamless integration of the architecture into conventional, OpenGL-like graphics ...
Weyrich, Tim +11 more
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Past and future of hardware and architecture
SOSP History Day 2015, 2015We start by looking back at 50 years of computer architecture, where philosophical debates on instruction sets (RISC vs. CISC, VLIW vs. RISC) and parallel architectures (NUMA vs clusters) were settled with billion dollar investments on both sides. In the second half, we look forward.
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A new hardware capability architecture
ACM SIGOPS Operating Systems Review, 1980In existing capability machines, such as the CAP and the Plessey 250, the programmer recognises two types of segment, one in which he keeps capabilities and one in which he keeps data words and instructions. The hardware provides two kinds of access, C-type and D-type; generally speaking, C-type access is used for capability segments and D-type access ...
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ACM SIGOPS Operating Systems Review, 1987
Programming Languages and Operating Systems introduce abstractions which allow the programmer to ignore details of an implementation. Support of an abstraction must not only concentrate on promoting the efficiency of an implementation, but also on providing the necessary guards against violations of the abstractions. In the frantic drive for efficiency
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Programming Languages and Operating Systems introduce abstractions which allow the programmer to ignore details of an implementation. Support of an abstraction must not only concentrate on promoting the efficiency of an implementation, but also on providing the necessary guards against violations of the abstractions. In the frantic drive for efficiency
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Hardware Architecture for Genetic Algorithms
2005In this paper, we propose an overall architecture for hardware implementation of genetic algorithms. The proposed architecture is independent of such specifics. It implements the fitness computation using a neural networks.
Nadia Nedjah, Luiza de Macedo Mourelle
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Hardware: The ERRIC Architecture
2016There is no doubt, system software support of computer resilience is incomplete when hardware does not have essential properties required to implement it. Luckily hardware with required support of recoverability and fault detection is available and described in full detail in Schagaev, Proceedings of the international multi-conference on computer ...
Igor Schagaev, Thomas Kaegi-Trachsel
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Hardware-Architecture and Computer Organisation
1973My general theme is the development of computer design at the University of Manchester with particular reference to our present system the MU5. As its name implies this is the fifth system designed at Manchester, the first coming into operation in 1951.
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2013
In the previous chapter, the architecture and operation for a MBC based generic reconfigurable framework was discussed in details. In this chapter, the focus is on a malleable hardware accelerator which leverages the memory based computing model for on-demand computation in an existing memory architecture.
Somnath Paul, Swarup Bhunia
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In the previous chapter, the architecture and operation for a MBC based generic reconfigurable framework was discussed in details. In this chapter, the focus is on a malleable hardware accelerator which leverages the memory based computing model for on-demand computation in an existing memory architecture.
Somnath Paul, Swarup Bhunia
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Hardware architecture of OFCE-HS for hardware implementation
SPIE Proceedings, 2011Optical flow algorithm proposed by Horn and Schunck (OFCE-HS) in 1981 was the first technique and one of the best performers for motion estimation. Attempts to implement OFCE-HS into real-time hardware have been performed by researchers. Hardware architecture of OFCE-HS proposed by Martin et al.
Ruzali Rustam +2 more
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Minicomputer hardware architecture
Proceedings of the IEEE, 1973After a general description of the major hardware elements of a minicomputer, the system is discussed from the viewpoint of a machine-language programmer. It is shown that the machine imposes certain constraints upon the programmer. These constraints are necessary in order to provide computation capability at a reasonable cost. In order to increase the
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