Results 31 to 40 of about 72,027 (265)

Is an Apple an Orange? A Large Language Model Benchmark for Candidate Term Extraction and Subclass Decisions Against Upper Ontologies in Engineering and Materials Science

Advanced Engineering Materials, EarlyView.
Building machine‐readable vocabularies for materials science is slow, expert‐driven work. This study benchmarks 13 large language models on two of its first steps: finding candidate terms in engineering articles and deciding where they belong in a class hierarchy.
Thomas Bjarsch, Maximilian Holland, Klaus Drechsler, Johannes Schilp   +3 more
wiley   +1 more source

A pseudo-softmax function for hardware-based high speed image classification

Scientific Reports, 2021
In this work a novel architecture, named pseudo-softmax, to compute an approximated form of the softmax function is presented. This architecture can be fruitfully used in the last layer of Neural Networks and Convolutional Neural Networks for ...
Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Alberto Nannarelli, Marco Re, Sergio Spanò   +6 more
doaj   +1 more source

A Practical Noise2Noise Denoising Pipeline for High‐Throughput Raman Spectroscopy

Advanced Engineering Materials, EarlyView.
A lightweight and reproducible denoising pipeline for high‐throughput Raman spectroscopy is introduced, based on a 1D convolutional autoencoder trained with a Noise2Noise strategy. Using only repeated short‐exposure acquisitions, the method suppresses stochastic noise without reference spectra, enabling reliable spectral reconstruction while preserving
David Martin‐Calle, Cesar Alvarez‐Llamas, Vincent Motto‐Ros, Christophe Dujardin, Jérémie Margueritat, David Rodney   +5 more
wiley   +1 more source

Fine grain algorithm parallelization on a hybrid control-flow and dataflow processor

Journal of Big Data
The execution time of a high-performance computing algorithm is influenced by various factors, including the algorithm's scalability, the selected hardware for processing elements, and the communication speed between these elements. This study utilizes a
Nenad Korolija
doaj   +1 more source

XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware

International Journal of Reconfigurable Computing, 2016
This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint ...
Gaurav Purohit, Kota Solomon Raju, Vinod Kumar Chaubey   +2 more
doaj   +1 more source

A SVPWM Hardware Architecture Based on FPGA and Its Computational Speed Optimization [PDF]

Zhengzhou Daxue xuebao. Gongxue ban
In order to improve the modulation speed of seven segment two-level SVPWM algorithm and reduce the use of logic resources, a hardware architecture of SVPWM based on FPGA was proposed. After inputting the reference voltage, the hardware architecture first
LIU Deping, XIN Yunchuan, LIU Zixu
doaj   +1 more source

Semantic Modeling in Materials Science and Engineering With Platform MaterialDigital Core Ontology 3.0

Advanced Engineering Materials, EarlyView.
The community‐driven Platform MaterialDigital Core Ontology (PMDco) 3.0 is introduced as a Basic Formal Ontology‐aligned semantic backbone for the processing–structure–properties paradigm in Materials Science and Engineering. Modular engineering, automated releases, and validation workflows are highlighted and key semantic patterns for materials ...
Markus Schilling, Philipp von Hartrott, Jörg Waitelonis, Thomas Hanke, Henk Birkholz, Hossein Beygi Nasrabadi, Khashayar Razghandi, Kamilla Zaripova, Felix Thonagel, Fabian Neuhaus, Martin Glauer, Lars Vogt, Harald Sack, Lutz Mädler, Bernd Bayerlein, Chris Eberl   +15 more
wiley   +1 more source

An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm

IEEE Access, 2019
In this paper we propose an efficient hardware architecture that implements the Q-Learning algorithm, suitable for real-time applications. Its main features are low-power, high throughput and limited hardware resources.
Sergio Spano, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re   +7 more
doaj   +1 more source

Software Controlled Low Cost Thermoelectric Energy Harvester for Ultra-Low Power Wireless Sensor Nodes

IEEE Access, 2020
General hardware architecture of an energy-harvested wireless sensor network node (EH-WSN) can be divided into power, sensing, computing and communication subsystems.
Michal Markiewicz, Piotr Dziurdzia, Tomasz Konieczny, Marek Skomorowski, Liliana Kowalczyk, Thomas Skotnicki, Pascal Urard   +6 more
doaj   +1 more source

Dedicated hardware architecture for localizing iris in VW images

Journal of King Saud University: Computer and Information Sciences, 2022
This study presents dedicated hardware for iris localization that can be used as a coprocessor in the development of real-time and low-cost embedded iris biometric systems.
Vineet Kumar, Abhijit Asati, Anu Gupta
doaj   +1 more source