Results 11 to 20 of about 72,027 (265)
SCALABLE ARCHITECTURE OF NETWORK SECURITY SYSTEMS
Современные информационные технологии и IT-образование, 2019 As a rule, certified means of ensuring network security are highly specialized complexes with a constant hardware and software platform. The main disadvantage of this architecture is the impossibility of transparent scaling of devices when the computing ...
Oleg Yu. Guzev, Ivan V. Chizhov
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Sensors, 2022 Deep neural networks have been deployed in various hardware accelerators, such as graph process units (GPUs), field-program gate arrays (FPGAs), and application specific integrated circuit (ASIC) chips.
Liang Chang, Xin Zhao, Jun Zhou
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Research and Implementation of an Embedded Hardware-Assisted Debugging Mechanism [PDF]
Jisuanji gongcheng, 2022 A series of independent instruction architecture chips(called GCXP in this paper) mainly use the hardware debugging mechanism based on scan chain reuse.Compared to mainstream commercial embedded chip products, the hardware modulation mechanism of ...
LIU Peng, LIU Jie, JIA Xun
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A novel FPGA implementation of Hough Transform for straight lane detection
Engineering Science and Technology, an International Journal, 2020 Hough Transform (HT) algorithm is commonly used for linear detection but requires huge memory and computational complexity. In this paper, we design an adapted hardware architecture of HT for straight lane lines detection.
Ismaïl El Hajjouji +3 more
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Sensors, 2023 Spectral congestion and modern consumer applications motivate radio technologies that efficiently cooperate with nearby users and provide several services simultaneously.
Hanguang Yu +10 more
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An Optimized Cyclic Weight Algorithm of (47, 24, 11) QR Code and Hardware Implementation
IEEE Access, 2018 This paper proposes an optimized cyclic weight (OCW) decoding algorithm based on novelty ideas. The OCW algorithm utilizes the properties of quadratic residue (QR) codes and the advantages of the syndrome-weight algorithm to facilitate fast decoding of ...
Jiye Huang +3 more
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Comparison of Three Smart Camera Architectures for Real-Time Machine Vision System
International Journal of Advanced Robotic Systems, 2013 This paper presents a machine vision system for real-time computation of distance and angle of a camera from a set of reference points located on a target board.
Abdul Waheed Malik +2 more
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Differentiable Neural Architecture, Mixed Precision and Accelerator Co-Search
IEEE Access, 2023 Quantization, effective Neural Network architecture, and efficient accelerator hardware are three important design paradigms to maximize accuracy and efficiency.
Krishna Teja Chitty-Venkata +4 more
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A High-Performance and Reconfigurable Hardware Architecture for FrodoKEM
Transactions on Cryptographic Hardware and Embedded SystemsFrodoKEM is an unstructured lattice-based post-quantum key encapsulation mechanism (KEM) renowned for its minimal algebraic structure and conservative security guarantees, offering strong confidence in long-term security.
Fu Yao +3 more
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Efficient BinDCT hardware architecture exploration and implementation on FPGA
Journal of Advanced Research, 2016 This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device.
Abdessalem Ben Abdelali +3 more
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