Results 1 to 10 of about 72,027 (265)
Neural Architecture Search and Hardware Accelerator Co-Search: A Survey
IEEE Access, 2021 Deep neural networks (DNN) are now dominating in the most challenging applications of machine learning. As DNNs can have complex architectures with millions of trainable parameters (the so-called weights), their design and training are difficult even for
Lukas Sekanina
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Mathematics, 2022 In this paper, the conceptualization of a control hardware architecture aimed to the implementation of integer- and fractional-order identification and control algorithms is presented.
Juan J. Gude, Pablo García Bringas
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A Low-Cost Multi-Sized HEVC Core Transform Using Time-Multiplexed DCT Architectures [PDF]
Journal of Operation and Automation in Power Engineering, 2022 High Efficiency Video Coding (HEVC) is one of the latest coding standards targeting high-resolution video contents. Due to the high complexity of the existing hardware implementation, this paper presents the low-cost and efficient DCT architectures for ...
R. Younesi, J. Rastegar, M. Rastgarpour
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A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium
Transactions on Cryptographic Hardware and Embedded Systems, 2021 The lattice-based CRYSTALS-Dilithium scheme is one of the three thirdround digital signature finalists in the National Institute of Standards and Technology Post-Quantum Cryptography Standardization Process.
Cankun Zhao +9 more
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Perspectives in Simulation Hardware and Software Architecture [PDF]
Modeling, Identification and Control, 1985 Historically, analog and hybrid computer systems have provided effective real-time solutions for the simulation of large dynamic systems. In the mid 1970s, ADI concluded that these systems were no longer adequate to meet the demands of larger, more ...
W.O. Grierson
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IEEE Access, 2022 Aiming at providing an efficient hardware architecture for generalized spatial modulation (GSM) multiple-input multiple-output (MIMO) systems, in this paper a COordinate Rotation DIgital Computer (CORDIC) -based symbol detector is proposed.
Hoang-Yang Lu +5 more
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Efficient Phase Unwrapping Architecture for Digital Holographic Microscopy
Sensors, 2011 This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM). A fast Fourier transform (FFT) based phase unwrapping algorithm providing a minimum squared error solution is ...
Wen-Jyi Hwang +2 more
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Hardware Architecture and Implementation of an AI Pet Robot
International Journal of Applied Sciences and Smart Technologies, 2020 The concept of AI companionship is gaining popularity in recent times. Ourproject is an attempt to create a robotic companion that can act just like apet.
Elton Lemos +2 more
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CLEI Electronic Journal, 2010 This work presents a dedicated hardware design for the Forward Quantization Module (Q module) of the H.264/AVC Video Coding Standard, using optimized multipliers.
Felipe Sampaio +3 more
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Low Power and High Speed DFT Architecture
Diyala Journal of Engineering Sciences, 2016 Discrete Fourier Transform (DFT) plays essential role in many signal processing applications. In this paper, novel hardware architecture is presented for DFT.
Ahmed K. Jameil
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