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Hardware enhanced security

Proceedings of the 2012 ACM conference on Computer and communications security, 2012
Building a secure computing system requires careful coordination among all layers in the system from hardware to software. Even if secure by itself, a higher layer protection mechanism may be bypassed if lower layer software or hardware is vulnerable. Additionally, hardware complements software through its efficiency, tamper resistance, etc. There have
Ruby Lee   +2 more
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Hardware-Level Secure Coding

IEEE Embedded Systems Letters
In this letter, a combined encryption and error-control coding scheme based on Turbo Codes (TC) is proposed to enhance the security of the transmission. It relies on Convolutional Encoders that operate over Galois Fields GF(4) and include variable encryption polynomials, whose coefficients are randomly selected every L steps from a set of optimal ...
Raúl Eduardo Lopresti   +1 more
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Hardware Enabled Security:

2023
Organizations employ a growing volume of machine identities, often numbering in the thousands or millions per organization. Machine identities, such as secret cryptographic keys, can be used to identify which policies need to be enforced for each machine. Centralized management of machine identities
Michael Bartock   +5 more
openaire   +1 more source

Hardware cyber security

Proceedings of the 2014 on International symposium on physical design, 2014
The attacks targeting hardware range from IP piracy to data theft to intentional hardware compromise and sabotage. Of particular concern are systemic, or combined, attacks that include both software and hardware elements: as the secure computing architectures, such as Intel TPM or ARM TrustZone, become more common, their hardware-based trust anchors ...
openaire   +1 more source

Hardware Security Modules

2013
Hardware Security Modules/(HSMs), also known as Tamper Resistant Security Modules (TRSMs), are devices dedicated to performing cryptographic functions such as data encryption/decryption, certificate management and calculation of specific values such as card verification values (CVVs) or Personal Identification Numbers (PINs).
Stathis Mavrovouniotis, Mick Ganley
openaire   +1 more source

Hardware Security Challenges

2010
This chapter discusses the problem of malicious hardware, or gateware, on FPGAs. Categories of malicious hardware, the problem of foundry trust, and attacks facilitated by malicious inclusions are presented. This chapter also explains the problem of covert channels on FPGAs, with a formal definition of a covert channel in general and a description of ...
Ted Huffmire   +5 more
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Hardware-Assisted Security

Proceedings of the 2017 Workshop on Attacks and Solutions in Hardware Security, 2017
Hardware security architectures and primitives are becoming increasingly important in practice providing trust anchors and trusted execution environment to protect modern IT systems, and particularly secure the insecure legacy software. Emerging applications, for instance in IoT area, increasingly involve large numbers of connected and heterogeneous ...
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Hardware Intrinsic Security

2010
Counterfeiting of electronic goods and stealing of valuable and sensitive data has become a massive problem for companies, the economy and even the security of modern societies. In order to deal with these issues more and more security measures have to be put in place both at the system level as well as the device level.
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Hardware-based security

Computer Fraud & Security, 2004
Abstract The Internet is a polluted place, infested by viruses and over-populated by unsolicited junk such as spam and popups. While in theory there exist all the tools we need to protect ourselves from these nuisances and risks, in practice it is impossible for most casual users and for many companies to steer clear of them.
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Hardware Security of CE Devices [Hardware Matters]

IEEE Consumer Electronics Magazine, 2017
In my previous columns, I have covered various topics, including the evolution of the intellectual property core industry, digital integrated circuit (IC) design flow, high-level perspectives on intellectual property (IP) cores, and the transient fault resiliency of IP cores.
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