Results 31 to 40 of about 526,457 (288)

Design and analysis of hardware Trojans in approximate circuits

Electronics Letters, 2022
Approximate computing can accept errors in computation systems to achieve better utilisation of hardware resources. Approximate computing has been successfully developed in integrated circuits, such as approximate arithemtic circuits and approximate ...
Yuqin Dou, Chenghua Wang, Chongyan Gu, Máire O'Neill, Weiqiang Liu   +4 more
doaj   +1 more source

Secure pseudo-random linear binary sequences generators based on arithmetic polynoms

, 2014
We present a new approach to constructing of pseudo-random binary sequences (PRS) generators for the purpose of cryptographic data protection, secured from the perpetrator's attacks, caused by generation of masses of hardware errors and faults.
A Omondi, B Schneier, B Yang, HL Garner, JA Hetagurov, JM Ortega, MA Soderstrand, OA Finko, OA Finko, VA Krasnobaev, VP Shmerko, WK Jenkins   +11 more
core   +1 more source

The Pains of Hardware Security: An Assessment Model of Real-World Hardware Security Attacks

IEEE Open Journal of the Industrial Electronics Society
From military applications to everyday devices, hardware (HW) security is more relevant than ever before. The supply chain of integrated circuits is global and involves multiple actors, which facilitate the implementation of various attacks.
Sofia Maragkou, Lukas Rappel, Hendrik Dettmer, Thilo Sauter, Axel Jantsch   +4 more
doaj   +1 more source

Heuristic Methods for Security Protocols

, 2009
Model checking is an automatic verification technique to verify hardware and software systems. However it suffers from state-space explosion problem. In this paper we address this problem in the context of cryptographic protocols by proposing a security ...
Nizamani, Qurat ul Ain, Tuosto, Emilio
core   +2 more sources

All‐in‐One Analog AI Hardware: On‐Chip Training and Inference with Conductive‐Metal‐Oxide/HfOx ReRAM Devices

Advanced Functional Materials, EarlyView.
An all‐in‐one analog AI accelerator is presented, enabling on‐chip training, weight retention, and long‐term inference acceleration. It leverages a BEOL‐integrated CMO/HfOx ReRAM array with low‐voltage operation (<1.5 V), multi‐bit capability over 32 states, low programming noise (10 nS), and near‐ideal weight transfer.
Donato Francesco Falcone, Victoria Clerico, Wooseok Choi, Tommaso Stecconi, Folkert Horst, Laura Bégon‐Lours, Matteo Galetta, Antonio La Porta, Nikhil Garg, Fabien Alibart, Bert Jan Offrein, Valeria Bragaglia   +11 more
wiley   +1 more source

Register transfer level hardware design information flow modeling and security verification method

Xibei Gongye Daxue Xuebao
Information flow analysis can effectively model the security behavior and security properties of hardware design. However, the existing gate level information flow analysis methods cannot deal with large-scale designs due to computing power and ...
QIN Maoyuan, HOU Jiaying, LI Jiale, TANG Shibo, TAI Yu   +4 more
doaj   +1 more source

Towards Energy-Efficient and Secure Computing Systems

Journal of Low Power Electronics and Applications, 2018
Countermeasures against diverse security threats typically incur noticeable hardware cost and power overhead, which may become the obstacle for those countermeasures to be applicable in energy-efficient computing systems.
Zhiming Zhang, Qiaoyan Yu
doaj   +1 more source

On the Security Goals of White-Box Cryptography

Transactions on Cryptographic Hardware and Embedded Systems, 2020
We discuss existing and new security notions for white-box cryptography and comment on their suitability for Digital Rights Management and Mobile Payment Applications, the two prevalent use-cases of white-box cryptography.
Estuardo Alpirez Bock, Alessandro Amadori, Chris Brzuska, Wil Michiels   +3 more
doaj   +1 more source

Parallel 3D Bioprinting on SLIPS‐Microarrays

Advanced Functional Materials, EarlyView.
This work introduces the first truly parallel 3D bioprinting method, enabling both the simultaneous fabrication of hundreds of cell laden hydrogel 3D structures and their HTS in individual liquid compartments. By integrating Digital Light Processing (DLP) stereolithography with functional micropatterns, the platform decouples printing time from array ...
Julius von Padberg, Julian A. Serna, Maike Schliephake, Pavel A. Levkin   +3 more
wiley   +1 more source

Hardware Trojan Detection and Mitigation in NoC using Key authentication and Obfuscation Techniques

Emitter: International Journal of Engineering Technology, 2022
Today's Multiprocessor System-on-Chip (MPSoC) contains many cores and integrated circuits. Due to the current requirements of communication, we make use of Network-on-Chip (NoC) to obtain high throughput and low latency.
Thejaswini P, Vivekananda G, Anu H, Priya R, Krishna Prasad B S, Nischay M   +5 more
doaj   +1 more source