Results 1 to 10 of about 430 (124)
Performance pathologies in hardware transactional memory [PDF]
Computer Architecture News, 2007 Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution. Previously proposed HTMs represent three points in this design space: lazy conflict detection, lazy version management, committer wins (LL); eager conflict detection, lazy version ...
Jayaram Bobba, Haris Volos, Luke Yen
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Improving Parallelism in Hardware Transactional Memory [PDF]
Transactions on Architecture and Code Optimization, 2018 Today’s hardware transactional memory (HTM) systems rely on existing coherence protocols, which implement a requester-wins strategy. This, in turn, leads to poor performance when transactions frequently conflict, causing them to resort to a non-speculative fallback path. Often, such a path severely limits parallelism.
Dave Dice +2 more
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Modularising Verification Of Durable Opacity [PDF]
Logical Methods in Computer Science, 2022 Non-volatile memory (NVM), also known as persistent memory, is an emerging paradigm for memory that preserves its contents even after power loss. NVM is widely expected to become ubiquitous, and hardware architectures are already providing support for ...
Eleni Bila +5 more
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Migration in Hardware Transactional Memory on Asymmetric Multiprocessor
IEEE Access, 2021 In this paper, a system is presented which implements transactions migration to an asymmetric multiprocessor in order to decrease the probability of conflicts and improve execution performance.
Zivojin Sustran, Jelica Protic
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Design and implementation of a cloud server based on hardware virtualization
工程科学学报, 2022 Traditional cloud computing is developed from a high-performance cluster. Every server in the high-performance cluster has its own resources, including a CPU, memory, a network, I/O (Input/Output), a power system, and a heat dissipation system.
Chen-ming ZHENG +5 more
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Hardware transactional persistent memory [PDF]
Proceedings of the International Symposium on Memory Systems, 2018 16 pages, 17 ...
Ellis Giles +2 more
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A Dynamically Adaptable Hardware Transactional Memory [PDF]
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010 Most Hardware Transactional Memory (HTM) implementations choose fixed version and conflict management policies at design time. While eager HTM systems store transactional state in-place in memory and resolve conflicts when they are produced, lazy HTM systems buffer the transactional state in specialized hardware and defer the resolution of conflicts ...
Lupon Navazo, Marc +2 more
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Refereeing conflicts in hardware transactional memory [PDF]
Proceedings of the 23rd international conference on Supercomputing, 2009 In the search for high performance, most transactional memory (TM) systems execute atomic blocks concurrently and must thus be prepared for data conflicts. The TM system also needs to choose a policy to decide when and how to manage the resulting contention.
Arrvindh Shriraman, Sandhya Dwarkadas
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Hardware transactional memory for GPU architectures [PDF]
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, 2011 Graphics processor units (GPUs) are designed to efficiently exploit thread level parallelism (TLP), multiplexing execution of 1000s of concurrent threads on a relatively smaller set of single-instruction, multiple-thread (SIMT) cores to hide various long latency operations.
Wilson W. L. Fung +3 more
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Hardware Transactions in Nonvolatile Memory [PDF]
, 2015 Hardware transactional memory (HTM) implementations already provide a transactional abstraction at HW speed in multi-core systems. The imminent availability of mature byte-addressable, nonvolatile memory (NVM) will provide persistence at the speed of accessing main memory.
Hillel Avni, Eliezer Levy, Avi Mendelson
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