Results 11 to 20 of about 449 (143)
Hardware acceleration of number theoretic transform for zk‐SNARK
Engineering Reports, EarlyView., 2023 An FPGA‐based hardware accelerator with a multi‐level pipeline is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. It can be flexibly scaled to different scales of FPGAs and has been equipped in the heterogeneous acceleration system with the help of HLS and OpenCL.
Haixu Zhao +6 more
wiley +1 more source
Intent Arabic text categorisation based on different machine learning and term frequency
IET Networks, EarlyView., 2022 Abstract The complexity of Internet network configurations has made managing networks a complicated undertaking. Intent‐Based Networking (IBN) is a potential solution to this issue. In contrast to conventional networks, where a concrete description of the settings typically conveys a network administrator's goal kept on each device, an administrator's ...
Mohammad Fadhil Mahdi +1 more
wiley +1 more source
An Analytical Model of Hardware Transactional Memory [PDF]
2017 IEEE 25th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), 2017 This paper investigates the problem of deriving a white box performance model of Hardware Transactional Memory (HTM) systems. The proposed model targets TSX, a popular implementation of HTM integrated in Intel processors starting with the Haswell family in 2013.An inherent difficulty with building white-box models of commercially available HTM systems ...
Daniel Castro 0004 +3 more
openaire +1 more source
DHTM: Durable Hardware Transactional Memory [PDF]
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), 2018 The emergence of byte-addressable persistent (non-volatile) memory provides a low latency and high bandwidth path to durability. However, programmers need guarantees on what will remain in persistent memory in the event of a system crash. A widely accepted model for crash consistent programming is ACID transactions, in which updates within a ...
Arpit Joshi +3 more
openaire +2 more sources
ParaTM: Transparent Embedding of Hardware Transactional Memory for Traditional Applications
IEEE Access, 2018 As the many-core processors become more prevalent, the parallelism degree of applications is rapidly increasing. It is well known that multi-thread approaches are an effective solution to improve performance by exploiting multiple cores.
Kangmin Lee, Heeseung Jo
doaj +1 more source
Transactional pre-abort handlers in hardware transactional memory [PDF]
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018 Commercially available hardware transactional memory (HTM) implementations resolve a number of potentially problematic situations by aborting a transaction, rather than add the hardware complexity needed to handle each situation more gracefully. In this paper we propose pre-abort handlers, a general-purpose mechanism that invokes a software handler ...
Sunjae Park +2 more
openaire +1 more source
Understanding and utilizing hardware transactional memory capacity [PDF]
Proceedings of the 2021 ACM SIGPLAN International Symposium on Memory Management, 2021 Hardware transactional memory (HTM) provides a simpler programming model than lock-based synchronization. However, HTM has limits that mean that transactions may suffer costly capacity aborts. Understanding HTM capacity is therefore critical. Unfortunately, crucial implementation details are undisclosed.
Zixian Cai +2 more
openaire +1 more source
Reinforcing Meltdown Attack by Using a Return Stack Buffer
IEEE Access, 2019 Meltdown is a microarchitectural side-channel attack that extracts sensitive data in the kernel space of operating systems (OSs). Meltdown deliberately creates transient executions by exploiting an out-of-order execution technique and obtains the ...
Taehyun Kim, Youngjoo Shin
doaj +1 more source
Reduced hardware transactions [PDF]
Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures, 2013 For many years, the accepted wisdom has been that the key to adoption of best-effort hardware transactions is to guarantee progress by combining them with an all software slow-path, to be taken if the hardware transactions fail repeatedly. However, all known generally applicable hybrid transactional memory solutions suffer from a major drawback: the ...
Matveev, Alexander, Shavit, Nir N.
openaire +3 more sources
Power Efficient Hardware Transactional Memory [PDF]
ACM Transactions on Architecture and Code Optimization, 2016 Transactional Memory (TM) is no longer just an academic interest as industry has started to adopt the idea in its commercial products. In this paper, we propose Dynamic Transaction Issue (DTI), a new scheme that can be easily implemented on top of existing Hardware TM (HTM) systems, provided additional messages.
Sang Wook Stephen Do, Michel Dubois 0001
openaire +1 more source