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Translation Validation of High-Level Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010The growing complexity of systems and their implementation into silicon encourages designers to look for ways to model designs at higher levels of abstraction and then incrementally build portions of these designs - automatically or manually - from these high-level specifications.
Sorin Lerner +2 more
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High-Level Synthesis for Low Power
1997The primary objective of high-level synthesis is to provide automatic ways of translating the behavioral specification of a digital system, under a given set of design constraints, into a register-transfer (RT) level description consisting of a (possibly partitioned) control unit and some computing (i.e., data-path) units [1,2].
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Testability Analysis in High-Level Synthesis
1999International ...
Bukovjan, Peter +2 more
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Parallelizing High-Level Synthesis: A Code Transformational Approach to High-Level Synthesis
2018Luciano Lavagno +2 more
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