Results 131 to 140 of about 1,369 (159)
Some of the next articles are maybe not open access.
Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism
2004Parallel architecture design and ILP architectures are important topics at the core of every parallel system, affecting the total system performance in fundamental ways. Instruction-Level Parallelism has for decades represented a foremost performance booster of leading edge computing systems.
Wolfgang Karl +3 more
openaire +2 more sources
Branch merging for effective exploitation of instruction-level parallelism
ACM SIGMICRO Newsletter, 1992In this paper, we propose a novel algorithm for merging branches in VLIW and superscalar architectures employing multi-way branch mechanisms. The branch merging problem is to find sets of branches that, can be merged and executed concurrently. The advantages of using branch merging are: (1) to reduce the number of stalls due to branches and (2) to ...
Chung-Ta King +2 more
openaire +2 more sources
Combining optimization for cache and instruction-level parallelism
Proceedings of the 1996 Conference on Parallel Architectures and Compilation Technique, 2002Current architectural trends in instruction-level parallelism (ILP) have significantly increased the computational power of microprocessors. As a result, the demands on the memory system have increased dramatically. Not only do compilers need to be concerned with finding ILP to utilize machine resources effectively, but they also need to be concerned ...
openaire +2 more sources
Topic 8 Parallel Computer Architecture and Instruction-Level Parallelism
2003Parallel computer architecture and instruction-level parallelism are hot topics at Euro-Par conferences, since these techniques are present in most contemporary computing systems. At Euro-Par 2003, 18 papers were submitted to the topic, from which 1 distinguished, 4 regular and 4 short papers were accepted.
Jean-Francois Collard +3 more
openaire +2 more sources
Reconfigurable Instruction-Level Parallel Processor Architecture
2003This paper proposes an instruction-level parallel (ILP) processor with architecture reconfigurability. The processor can employ the optimal architecture to applications without loosing generality. Instruction-level parallelism is achieved by expanding the number of PUs depending on its load. Required features of reconfigurable hardware devices for such
Toshiyuki Ito +4 more
openaire +2 more sources
Parallelism of intestinal secretory IgA shapes functional microbial fitness
Nature, 2021Tim Rollenske +2 more
exaly
Genome-wide parallelism underlies contemporary adaptation in urban lizards
Proceedings of the National Academy of Sciences of the United States of America, 2023Shane C Campbell-Staton +2 more
exaly
Intercontinental genomic parallelism in multiple three-spined stickleback adaptive radiations
Nature Ecology and Evolution, 2020Isabel Santos Magalhaes +2 more
exaly
Molecular Parallelism Underlies Convergent Highland Adaptation of Maize Landraces
Molecular Biology and Evolution, 2021Emily B Josephs +2 more
exaly