Results 1 to 10 of about 10,270,316 (283)

A Programmable Crypto-Processor for National Institute of Standards and Technology Post-Quantum Cryptography Standardization Based on the RISC-V Architecture. [PDF]

Sensors (Basel), 2023
Lee J, Kim W, Kim JH.
europepmc   +1 more source

Optimized Hardware-Software Co-Design for Kyber and Dilithium on RISC-V SoC FPGA

Transactions on Cryptographic Hardware and Embedded Systems
Kyber and Dilithium are both lattice-based post-quantum cryptography (PQC) algorithms that have been selected for standardization by the American National Institute of Standards and Technology (NIST). NIST recommends them as two primary algorithms to be
Tengfei Wang, Chi Zhang, Xiaolin Zhang, Dawu Gu, Pei Cao   +4 more
doaj   +1 more source

DITES: A Lightweight and Flexible Dual-Core Isolated Trusted Execution SoC Based on RISC-V. [PDF]

Sensors (Basel), 2022
Chen Y, Chen H, Chen S, Han C, Ye W, Liu Y, Zhou H.   +6 more
europepmc   +1 more source

Design of Hardware Accelerators for Optimized and Quantized Neural Networks to Detect Atrial Fibrillation in Patch ECG Device with RISC-V. [PDF]

Sensors (Basel), 2023
Hoyer I, Utz A, Lüdecke A, Kappert H, Rohr M, Antink CH, Seidl K.   +6 more
europepmc   +1 more source

Using Dynamic-Length Vector Operations to Efficiently Emulate Fixed-Length Vector Operations

Современные информационные технологии и IT-образование
Using vector registers can significantly enhance processor performance, especially in tasks that involve parallel data processing. To ensure code portability across different architectures, developers often use third-party libraries.
Konstantin Vladimirov, Ivan Tetyushkin
doaj   +1 more source

A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System. [PDF]

Sensors (Basel), 2021
Zhang H, Wu X, Du Y, Guo H, Li C, Yuan Y, Zhang M, Zhang S.   +7 more
europepmc   +1 more source

Epileptic Seizure Detection on an Ultra-Low-Power Embedded RISC-V Processor Using a Convolutional Neural Network. [PDF]

Biosensors (Basel), 2021
Bahr A, Schneider M, Francis MA, Lehmann HM, Barg I, Buschhoff AS, Wulff P, Strunskus T, Faupel F.   +8 more
europepmc   +1 more source

Spike-RISC: Algorithm/ISA Co-Optimization for Efficient SNNs on RISC-V

IEEE Access
Artificial intelligence has proven its benefits in many domains. Yet, traditional deep learning models are still too energy and compute-intensive for resource-constrained edge environments.
Ipek Akdeniz, Sandy A. Wasif, Paul R. Genssler, Hussam Amrouch   +3 more
doaj   +1 more source

CRYPHTOR: A Memory-Unified NTT-Based Hardware Accelerator for Post-Quantum CRYSTALS Algorithms

IEEE Access
This paper presents the design and FPGA implementation of a hardware accelerator for the Post-Quantum CRYSTALS-Kyber and CRYSTALS-Dilithium algorithms, named CRYPHTOR (CRYstals Polynomial HW acceleraTOR).
Stefano Di Matteo, Ivan Sarno, Sergio Saponara   +2 more
doaj   +1 more source

MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI

IEEE Open Journal of Circuits and Systems
Deploying deep neural networks (DNNs) on resource-constrained IoT devices remains a challenging problem, often requiring hardware modifications tailored to individual AI models.
M. Ajay Kumar, Cian O'Mahoney, Pedro Kreutz Werle, Shreejith Shanker, Dimitrios S. Nikolopoulos, Bo Ji, Hans Vandierendonck, Deepu John   +7 more
doaj   +1 more source