Results 31 to 40 of about 10,270,316 (283)

Return-Oriented Programming on RISC-V [PDF]

Proceedings of the 15th ACM Asia Conference on Computer and Communications Security, 2020
This paper provides the first analysis on the feasibility of Return-Oriented Programming (ROP) on RISC-V, a new instruction set architecture targeting embedded systems. We show the existence of a new class of gadgets, using several Linear Code Sequences And Jumps (LCSAJ), undetected by current Galileo-based ROP gadget searching tools.
Georges-Axel Jaloyan, Konstantinos Markantonakis, Raja Naeem Akram, David Robin, Keith Mayes, David Naccache   +5 more
openaire   +2 more sources

RISC-V: #AlphanumericShellcoding

CoRR, 2019
25 pages, originally published at WOOT ...
Hadrien Barral, Rémi Géraud-Stewart, Georges-Axel Jaloyan, David Naccache   +3 more
openaire   +4 more sources

Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms

Cryptography, 2022
The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient implementation of common algorithms.
Görkem Nişancı, Paul G. Flikkema, Tolga Yalçın   +2 more
doaj   +1 more source

Backporting RISC-V Vector Assembly

, 2023
Leveraging vectorisation, the ability for a CPU to apply operations to multiple elements of data concurrently, is critical for high performance workloads. However, at the time of writing, commercially available physical RISC-V hardware that provides the RISC-V vector extension (RVV) only supports version 0.7.1, which is incompatible with the latest ...
Joseph K. L. Lee, Maurice Jamieson, Nick Brown 0002   +2 more
openaire   +4 more sources

Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective [PDF]

, 2023
Vitamin-V is a project funded under the Horizon Europe program for the period 2023-2025. The project aims to create a complete open-source software stack for RISC-V that can be used for cloud services.
Otero Calviño, Beatriz, Alonso García, Martí, Andreu Gerique, David, Rodríguez Luna, Eva, Di Carlo, Stefano, Papadimitriou, George, Karakostas, Vasileios, Chenet, Cristiano, Gizopoulos, Dimitris, Canal Corretger, Ramon, Costa Prats, Juan José, Gironès, Andreu, Savino, Alessandro   +12 more
core   +1 more source

A Unified PUF and Crypto Core Exploiting the Metastability in Latches

Future Internet, 2022
Hardware acceleration of cryptography algorithms represents an emerging approach to obtain benefits in terms of speed and side-channel resistance compared to software implementations.
Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham   +5 more
doaj   +1 more source

Generic Tagging for RISC-V Binaries

CoRR, 2022
With the widespread popularity of RISC-V -- an open-source ISA -- custom hardware security solutions targeting specific defense needs are gaining popularity. These solutions often require specialized compilers that can insert metadata (called tags) into the generated binaries, and/or extend the RISC-V ISA with new instructions.
David Demicco, Matthew Cole, Gokturk Yuksek, Ravi Theja Gollapudi, Aravind Prakash, Kanad Ghose, Zerksis Umrigar   +6 more
openaire   +3 more sources

A Framework for Fault Tolerance in RISC-V

2022 IEEE Intl Conf on Dependable, Autonomic and Secure Computing, Intl Conf on Pervasive Intelligence and Computing, Intl Conf on Cloud and Big Data Computing, Intl Conf on Cyber Science and Technology Congress (DASC/PiCom/CBDCom/CyberSciTech), 2022
Microcontrollers require protection against transient and permanent faults when being utilized for safety-critical and highly reliable applications. Fail safe Dual Core Lockstep architectures are widely used in the automotive domain; the aerospace domain utilizes fail functional TMR or higher redundancy.
Dörflinger, Alexander, Kleinbeck, Benedikt, Albers, Mark, Michalik, Harald, Moya, Martin   +4 more
openaire   +3 more sources

The design of scalar AES Instruction Set Extensions for RISC-V

Transactions on Cryptographic Hardware and Embedded Systems, 2020
Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardized ISE.
Ben Marshall, G. Richard Newell, Dan Page, Markku-Juhani O. Saarinen, Claire Wolf   +4 more
doaj   +3 more sources

Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype

Journal of Low Power Electronics and Applications, 2022
RISC-V is a modern Instruction Set Architecture (ISA) that, by its open nature in combination with a clean and modular design, has enormous potential to become a game changer in the Internet of Things (IoT) era. Recently, SystemC-based Virtual Prototypes
Pascal Pieper, Vladimir Herdt, Rolf Drechsler   +2 more
doaj   +1 more source