Results 31 to 40 of about 24,258 (296)
RISC-V: #AlphanumericShellcoding
, 2019 25 pages, originally published at WOOT ...
Barral, Hadrien +3 more
openaire +2 more sources
A Survey on RISC-V-Based Machine Learning Ecosystem
Information, 2023 In recent years, the advancements in specialized hardware architectures have supported the industry and the research community to address the computation power needed for more enhanced and compute intensive artificial intelligence (AI) algorithms and ...
Stavros Kalapothas +4 more
doaj +1 more source
BRISC-V emulator: a standalone, installation-free, browser-based teaching tool [PDF]
, 2020 Many computer organization and computer architecture classes have recently started adopting the RISC-V architecture as an alternative to proprietary RISC ISAs and architectures.
Isakov, Mihailo, Kinsy, Michel A.
core
High throughput accelerator interface framework for a linear time-multiplexed FPGA overlay [PDF]
, 2020 Coarse-grained FPGA overlays improve design productivity through software-like programmability and fast compilation. However, the effectiveness of overlays as accelerators is dependent on suitable interface and programming integration into a typically ...
Fahmy, Suhaib A. +4 more
core +1 more source
An ultra-low-power processor pipeline-structure
Dianzi Jishu Yingyong, 2019 With the rapid development of communication and chip technology, IoT will be an important part of the next generation of information technology, a powerful driving force to promote the intelligent process of our lives. Among the IoT terminal applications,
Deng Tianchuan, Hu Zhenbo
doaj +1 more source
CIDPro: Custom Instructions for Dynamic Program Diversification
, 2018 Timing side-channel attacks pose a major threat to embedded systems due to their ease of accessibility. We propose CIDPro, a framework that relies on dynamic program diversification to mitigate timing side-channel leakage.
Biswas, Arnab Kumar +4 more
core +1 more source
Secure Silicon: Towards Virtual Prototyping [PDF]
, 2016 Evaluating security vulnerabilities of software implementations at design step is of primary importance for applications developers, while it has received litte attention from scientific communauty.
Sauvage, Laurent +2 more
core +1 more source
The RISC-V FPGA (RVfpga) Teaching Package
IEEE AccessRISC-V is a free and open-standard ISA based on RISC principles, allowing anyone to design, manufacture, and sell RISC-V chips and software. Its flexibility and growing ecosystem have made it popular in research, education, and industry, increasing the ...
Daniel Chaver +17 more
doaj +1 more source
ChaCha20–Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3
Cryptography, 2022 Transport Layer Security (TLS) provides a secure channel for end-to-end communications in computer networks. The ChaCha20–Poly1305 cipher suite is introduced in TLS 1.3, mitigating the sidechannel attacks in the cipher suites based on the Advanced ...
Ronaldo Serrano +4 more
doaj +1 more source
A Scalable, Portable, and Memory-Efficient Lock-Free FIFO Queue [PDF]
, 2019 We present a new lock-free multiple-producer and multiple-consumer (MPMC) FIFO queue design which is scalable and, unlike existing high-performant queues, very memory efficient.
Nikolaev, Ruslan
core +2 more sources