Results 21 to 30 of about 7,414,880 (281)

RISC-V: #AlphanumericShellcoding

CoRR, 2019
25 pages, originally published at WOOT ...
Hadrien Barral, Rémi Géraud-Stewart, Georges-Axel Jaloyan, David Naccache   +3 more
openaire   +3 more sources

Return-Oriented Programming on RISC-V [PDF]

Proceedings of the 15th ACM Asia Conference on Computer and Communications Security, 2020
This paper provides the first analysis on the feasibility of Return-Oriented Programming (ROP) on RISC-V, a new instruction set architecture targeting embedded systems. We show the existence of a new class of gadgets, using several Linear Code Sequences And Jumps (LCSAJ), undetected by current Galileo-based ROP gadget searching tools.
Georges-Axel Jaloyan, Konstantinos Markantonakis, Raja Naeem Akram, David Robin, Keith Mayes, David Naccache   +5 more
openaire   +2 more sources

De-RISC: A complete RISC-V based space-grade platform [PDF]

, 2022
The H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain such as: (1) higher performance than that of monocore and basic multicore space-grade ...
Nicolau Gallego, Vicente, Cabo Pitarch, Guillem, García Vilanova, Antonio, Masmano Tello, Miguel, Bas Jalón, Francisco, Malatesta, Fabio, Abella Ferrer, Jaume, Benedicte Illescas, Pedro, Ribes, Stefano, Gómez Molinero, Paco, Andersson, Jan, Alcaide Portet, Sergi, Mazzocchetti, Fabio, Le Rhun, Jimmy, Wessman, Nils-Johan   +14 more
core   +1 more source

Backporting RISC-V Vector Assembly

, 2023
Leveraging vectorisation, the ability for a CPU to apply operations to multiple elements of data concurrently, is critical for high performance workloads. However, at the time of writing, commercially available physical RISC-V hardware that provides the RISC-V vector extension (RVV) only supports version 0.7.1, which is incompatible with the latest ...
Joseph K. L. Lee, Maurice Jamieson, Nick Brown 0002   +2 more
openaire   +2 more sources

Generic Tagging for RISC-V Binaries

CoRR, 2022
With the widespread popularity of RISC-V -- an open-source ISA -- custom hardware security solutions targeting specific defense needs are gaining popularity. These solutions often require specialized compilers that can insert metadata (called tags) into the generated binaries, and/or extend the RISC-V ISA with new instructions.
David Demicco, Matthew Cole, Gokturk Yuksek, Ravi Theja Gollapudi, Aravind Prakash, Kanad Ghose, Zerksis Umrigar   +6 more
openaire   +2 more sources

Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype

Journal of Low Power Electronics and Applications, 2022
RISC-V is a modern Instruction Set Architecture (ISA) that, by its open nature in combination with a clean and modular design, has enormous potential to become a game changer in the Internet of Things (IoT) era. Recently, SystemC-based Virtual Prototypes
Pascal Pieper, Vladimir Herdt, Rolf Drechsler   +2 more
doaj   +1 more source

The design of scalar AES Instruction Set Extensions for RISC-V

Transactions on Cryptographic Hardware and Embedded Systems, 2020
Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardized ISE.
Ben Marshall, G. Richard Newell, Dan Page, Markku-Juhani O. Saarinen, Claire Wolf   +4 more
doaj   +3 more sources

Design of SoC System for Convolution Acceleration Based on RISC-V Processor [PDF]

Jisuanji gongcheng, 2021
To improve the computation and energy efficiency of Convolutional Neural Network(CNN),this paper proposes a convolution accelerator with 8 bit fixed-point data as input.The accelerator supports common CNN calculations,including activation,Batch ...
ZHANG Kunning, ZHAO Shuo, HE Hu, DENG Ning, YANG Xu
doaj   +1 more source

A RISC-V Overview: Technical Details and Impact on the Industry [PDF]

, 2022
openIl mercato delle architetture fino ad ora è stato dominato da x86 nel settore computing e da Arm nel mercato embedded, tuttavia le esigenze stanno cambiando soprattutto grazie alla crescita di applicazioni avanzate come la computazione ad altre ...
BOLZONELLO, ENRICO
core  

A Framework for Fault Tolerance in RISC-V

2022 IEEE Intl Conf on Dependable, Autonomic and Secure Computing, Intl Conf on Pervasive Intelligence and Computing, Intl Conf on Cloud and Big Data Computing, Intl Conf on Cyber Science and Technology Congress (DASC/PiCom/CBDCom/CyberSciTech), 2022
Microcontrollers require protection against transient and permanent faults when being utilized for safety-critical and highly reliable applications. Fail safe Dual Core Lockstep architectures are widely used in the automotive domain; the aerospace domain utilizes fail functional TMR or higher redundancy.
Dörflinger, Alexander, Kleinbeck, Benedikt, Albers, Mark, Michalik, Harald, Moya, Martin   +4 more
openaire   +2 more sources