Results 11 to 20 of about 7,414,880 (281)

Hypervisor Extension for a RISC-V Processor [PDF]

CoRR, 2023
This work is partially supported by the DRAC (IU16-011591), the HORIZON Vitamin-V (101093062) and the Computación de Altas Prestaciones VIII (PID2019-107255GB) projects.
Gauchola Vilardell, Jaume, Costa Prats, Juan José, Morancho Llena, Enrique, Canal Corretger, Ramon, Carril Gil, Xavier, Doblas Font, Max, Otero Calviño, Beatriz, Pajuelo González, Manuel Alejandro, Rodríguez Luna, Eva, Salamero Sanz, Javier, Verdú Mulà, Javier   +10 more
core   +5 more sources

Functional Verification of a RISC-V Vector Accelerator

IEEE Design & Test, 2023
We present the functional verification efforts for an academic RISC-V based vector accelerator, successfully taped-out in the context of the European Processor Initiative. For our novel RISC-V based decoupled vector accelerator, we built a verification infrastructure consisting of a UVM environment, performing step by step co-simulation of all vector ...
Víctor Jiménez, Mario Rodríguez, Marc Domínguez, Josep Sans, Ivan Diaz, Luca Valente, Vito Luca Guglielmi, Josue V. Quiroga, R. Ignacio Genovese, Nehir Sönmez, Oscar Palomar, Miquel Moretó   +11 more
openaire   +5 more sources

Vitamin-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services [PDF]

, 2023
Vitamin-V is a 2023-2025 Horizon Europe project that aims to develop a complete RISC-V open-source software stack for cloud services with comparable performance to the cloud-dominant x86 counterpart and a powerful virtual execution environment for ...
I. Papaefstathiou, A. Arelakis, J. L. Berral, Y. Nikolakopoulos, A. Call, V. Karakostas, A. Torregrosa, K. Nikas, J. Costa, E. Rodríguez, R. Canal, A. Rigo, F. Lubrano, A. Scionti, D. Gizopoulos, D. Pnevmatikatos, G. Papadimitriou, J. M. Arnau, A. Savino, N. Tampouratzis, S. Di Carlo, D. Raho, B. Otero   +22 more
core   +3 more sources

LLVM RISC-V RV32X Graphics Extension Support and Characteristics Analysis of Graphics Programs

IEEE Access, 2023
In recent years, virtual reality technology has become the dominant means of human-computer interaction, with computer graphics rendering technology being a crucial component in realizing virtual reality experiences.
Peng Wang, Zhi-Bin Yu
doaj   +1 more source

Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective [PDF]

, 2023
Vitamin-V is a project funded under the Horizon Europe program for the period 2023-2025. The project aims to create a complete open-source software stack for RISC-V that can be used for cloud services.
Otero Calviño, Beatriz, Alonso García, Martí, Andreu Gerique, David, Rodríguez Luna, Eva, Di Carlo, Stefano, Papadimitriou, George, Karakostas, Vasileios, Chenet, Cristiano, Gizopoulos, Dimitris, Canal Corretger, Ramon, Costa Prats, Juan José, Gironès, Andreu, Savino, Alessandro   +12 more
core   +1 more source

Computer Engineering Education Experiences with RISC-V Architectures—From Computer Architecture to Microcontrollers

Journal of Low Power Electronics and Applications, 2022
With the growing popularity of RISC-V and various open-source released RISC-V processors, it is now possible for computer engineers students to explore this simple and relevant architecture, and also, these students can explore and design a ...
Peter Jamieson, Huan Le, Nathan Martin, Tyler McGrew, Yicheng Qian, Eric Schonauer, Alan Ehret, Michel A. Kinsy   +7 more
doaj   +1 more source

De-RISC: the First RISC-V space-grade platform for safety-critical systems [PDF]

, 2021
The increasing needs for performance in the space domain for highly autonomous systems calls for more powerful space MPSoCs and appropriate hypervisors to master them.
Nicolau Gallego, Vicente, Trilla Rodríguez, David, Cabo Pitarch, Guillem, Masmano Tello, Miguel, Bas Jalón, Francisco, Lorenzo Ortega, Rubén, Malatesta, Fabio, Abella Ferrer, Jaume, Gómez Molinero, Paco, Andersson, Jan, Sala Sucarrats, Oriol, Le Rhun, Jimmy, Wessman, Nils-Johan   +12 more
core   +1 more source

Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

IEEE Access, 2020
This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA).
Nguyen My Qui, Chang Hong Lin, Poki Chen
doaj   +1 more source

Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms

Cryptography, 2022
The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient implementation of common algorithms.
Görkem Nişancı, Paul G. Flikkema, Tolga Yalçın   +2 more
doaj   +1 more source

A Unified PUF and Crypto Core Exploiting the Metastability in Latches

Future Internet, 2022
Hardware acceleration of cryptography algorithms represents an emerging approach to obtain benefits in terms of speed and side-channel resistance compared to software implementations.
Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham   +5 more
doaj   +1 more source