Results 41 to 50 of about 24,258 (296)

Vector processing-aware advanced clock-gating techniques for low-power fused multiply-add [PDF]

, 2018
The need for power efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a retailoring for the mobile market that they are entering now ...
Cristal Kestelman, Adrián, Palomar Pérez, Óscar, Ratkovic, Ivan, Stanic, Milan, Unsal, Osman Sabri, Valero Cortés, Mateo   +5 more
core   +2 more sources

Uncovering the Origin of Efficiency Roll‐Off in TADF OLEDs

Advanced Functional Materials, EarlyView.
OLEDs based on thermally activated delayed fluorescent (TADF) materials often suffer from a severe drop in efficiency at high brightness levels. This work presents a technique to uncover the source of this efficiency drop, and quantifies the exciton‐exciton and exciton‐polaron annihilation processes responsible for efficiency losses in our TADF OLEDs ...
Liam G. King, Kou Yoshida, Arvydas Ruseckas, Ifor D. W. Samuel   +3 more
wiley   +1 more source

CodeTrolley: Hardware-Assisted Control Flow Obfuscation [PDF]

, 2019
Many cybersecurity attacks rely on analyzing a binary executable to find exploitable sections of code. Code obfuscation is used to prevent attackers from reverse engineering these executables.
Boskov, Novak, Isakov, Mihailo, Kinsy, Michel A.   +2 more
core   +1 more source

FAC-V: An FPGA-Based AES Coprocessor for RISC-V

Journal of Low Power Electronics and Applications, 2022
In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads.
Tiago Gomes, Pedro Sousa, Miguel Silva, Mongkol Ekpanyapong, Sandro Pinto   +4 more
doaj   +1 more source

HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA

, 2017
Heterogeneous embedded systems on chip (HESoCs) co-integrate a standard host processor with programmable manycore accelerators (PMCAs) to combine general-purpose computing with domain-specific, efficient processing capabilities.
Benini, Luca, Capotondi, Alessandro, Kurth, Andreas, Marongiu, Andrea, Vogel, Pirmin   +4 more
core   +1 more source

Per-Core DVFS with Switched-Capacitor Converters for Energy Efficiency in Manycore Processors [PDF]

, 2015
Integrating multiple power converters on-chip improves energy efficiency of manycore architectures. Switched-capacitor (SC) dc-dc converters are compatible with conventional CMOS processes, but traditional implementations suffer from limited conversion ...
Alon, E, Asanović, K, Bailey, S, Blagojević, M, Jevtić, R, Le, HP, Nikolić, B   +6 more
core   +1 more source

Neuromorphic Electronics for Intelligence Everywhere: Emerging Devices, Flexible Platforms, and Scalable System Architectures

Advanced Materials, EarlyView.
The perspective presents an integrated view of neuromorphic technologies, from device physics to real‐time applicability, while highlighting the necessity of full‐stack co‐optimization. By outlining practical hardware‐level strategies to exploit device behavior and mitigate non‐idealities, it shows pathways for building efficient, scalable, and ...
Kapil Bhardwaj, Roshni Satheesh Babu, Yuxin Xia, Eva Bestelink, Radu Sporea, Nikos Hastas, Ioannis Zeimpekis, Dimitra G. Georgiadou, Sayani Majumdar   +8 more
wiley   +1 more source

Highly Efficient Mechanochromic Thermally Activated Delayed Fluorescence in the Deep Red to Near‐Infrared in Copper(I) [2.2]Isoindolinophanyl‐Carbene Carbazolates

Angewandte Chemie, EarlyView.
Electrophilic [2.2]isoindolinophanyl‐based carbene iPC has been employed as charge‐transfer acceptor ligand in a series of [Cu(iPC)(carbazolate)], which show mechanochromism and environment‐dependent luminescence due to intermolecular C─‐H‐π interactions.
André M. T. Muthig, Sabyasachi Maity, Andreas Prüfer, Justin Krieger, Andrei Belyaev, Jan‐Benedikt Weiß, Sebastian Henke, Benjamin Hupp, Björn Ewald, Jens Pflaum, Andreas Steffen   +10 more
wiley   +2 more sources

Toward Secure RISC-V Microarchitecture: Vulnerability Classes and Defenses

IEEE Access
RISC-V is an open instruction set architecture that enables a wide range of processor implementations across academia and industry. While its architectural simplicity and extensibility support rapid innovation, RISC-V processors exhibit ...
Mahreen Khan, Maria Mushtaq, Renaud Pacalet, Ludovic Apvrille   +3 more
doaj   +1 more source

From FPGA to ASIC: A RISC-V processor experience [PDF]

, 2019
This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ...
Rojas Morales, Carlos
core   +1 more source