Results 51 to 60 of about 10,270,316 (283)
A Survey on RISC-V-Based Machine Learning Ecosystem
Information, 2023 In recent years, the advancements in specialized hardware architectures have supported the industry and the research community to address the computation power needed for more enhanced and compute intensive artificial intelligence (AI) algorithms and ...
Stavros Kalapothas +4 more
doaj +1 more source
This project makes a port of ZeOS, a monolithic operating system developed for the Intel 80386 architecture, to the RISC-V arquitecture. ZeOs finds implemented, among others, functionalities such as process management, memory management, interruptions and levels of privilege.
Barreto Tomeo, Xavier
openaire +2 more sources
, 2021 Operativsystemet Plan 9 har blitt tilpasset til å kjøre på mange instruksjonssettarkitekturer (ISAer) siden det ble introdusert på 1980-tallet. ISA-familien RISC-V er en stadig mer populær åpen standard egnet for et bredt spektrum av datasystemer.
Slettemark, Aksel Hauge
core +1 more source
Analysis on the Possibility of RISC-V Adoption [PDF]
, 2020 As the interface between hardware and software, Instruction Set Architectures (ISAs) play a key role in the operation of computers. While both hardware and software have continued to evolve rapidly over time, ISAs have undergone minimal change. Since its
Scott, Ian,, Scott, Ian, Ian Scott
core +1 more source
Protocol for quantifying miRNA trafficking across the endosomal membrane
FEBS Open Bio, EarlyView.An in vitro protocol measures miRNA uptake into endosomes isolated from mammalian cell extracts, which are free of subcellular contaminants. Performed at 37 °C in the presence of ATP, it ensures the import of single‐stranded miRNA into the endosomal lumen.
Syamantak Ghosh +2 more
wiley +1 more source
Implementation of RISC-V Processor [PDF]
ITM Web of ConferencesThis work focuses on implementation/designing the RISC-V Processor with optimized pipeline throughput, cache hit rate, and dynamic instruction scheduling to enhance the processing speed and energy efficiency. RISC-V extension used to support the tasks in
Saiprathyusha P., Chandrasekhar C.
doaj +1 more source
Holistic RISC-V Virtualization
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023 This work describes our efforts to provide a holistic hardware RISC-V virtualization SoC based on the CVA6 core. At the core level, we implemented hardware support for virtualization through the ratified Hypervisor instruction set architecture (ISA) extension version 1.0.
Bruno Sá +4 more
openaire +3 more sources
Annals of Clinical and Translational Neurology, EarlyView.ABSTRACT Objectives We aimed to determine the frequency of subclinical optic nerve (ON) lesions using MRI, optical coherence tomography (OCT), and visual evoked potentials (VEP) in radiologically isolated syndrome (RIS), and to assess their diagnostic and prognostic significance.
Christine Lebrun‐Frenay +13 more
wiley +1 more source
Advanced Functional Materials, EarlyView.High‐performing near‐infrared (NIR) organic light‐emitting diodes are demonstrated using an efficient and stable 800 nm‐emissive organic radical and a thermally activated delayed fluorescence (TADF) host. TADF‐assisted exciton generation combined with improved charge transport enables high external quantum efficiency (>8%), high radiance (>70,000 mW sr−
Hwan‐Hee Cho +6 more
wiley +1 more source
Optimized Software Implementation of Keccak, Kyber, and Dilithium on RV{32,64}IM{B}{V}
Transactions on Cryptographic Hardware and Embedded SystemsWith the standardization of NIST post-quantum cryptographic (PQC) schemes, optimizing these PQC schemes across various platforms presents significant research value. While most existing software implementation efforts have concentrated on ARM platforms,
Jipeng Zhang +3 more
doaj +1 more source