Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System
The open-source and customizable features of the RISC-V Instruction Set Architecture (ISA) have facilitated its rapid adoption since its publication in 2011.
Binh Kieu-do-Nguyen +7 more
doaj +1 more source
A Memristor‐Based In‐Memory Computing System‐on‐Chip with Efficient Depthwise Convolution
We present a memristor‐based in‐memory computing (IMC) architecture that enables efficient depthwise convolution (DWC) acceleration. Fabricated in a system‐on‐chip with crossbar arrays, the design improves memory utilization. Experimental validation demonstrates the first hardware acceleration of DWC in IMC, achieving a digital comparable inference ...
Wenhao Song +21 more
wiley +1 more source
Enabling Syscall Intercept for RISC-V
The European Union technological sovereignty strategy centers around the RISC-V Instruction Set Architecture, with the European Processor Initiative leading efforts to build production-ready processors. Focusing on realizing a functional RISC-V ecosystem, the BZL initiative (www.bzl.es) is making an effort to create a software stack along with the ...
Petar Andric, Aaron Call, Ramon Nou
openaire +2 more sources
RISC-V CO-PROCESSOR UNIT FOR IMNPU SPECIFICATIONS, FUNCTIONAL SAFE RISC-V HOST CORE SPECIFICATIONS
The objective of deliverable 3.1 (D3.1) “RISC-V co-processor unit for IMNPU specifications, functional safe RISC-V host core specifications” is to define and provide the specifications of the two RISC-V based components in the NeuroSoC system: - the RISC-
Daniel Gracia Pérez +1 more
core +1 more source
Heterogeneous computing at INFN-T1 [PDF]
At INFN-T1 we recently acquired some nodes with ARM and RISC-V CPUs to understand the experiment level of readiness on new hardware solutions and to test our production pipelines. After some initial testing, ARM resources entered the standard farm, since
Chierici Andrea +4 more
doaj +1 more source
The Role of miRNAs in Chicken Immune Regulation and Prospects for Disease‐Resistant Breeding
A schematic workflow illustrating the screening of disease‐resistant miRNAs and the generation of miRNA‐based disease‐resistant chickens via PGC‐mediated germline genome editing. ABSTRACT MicroRNAs (miRNAs) are emerging as pivotal regulators of the immune system, playing a decisive role in shaping disease resistance in chicken.
Qiangzhou Wang +10 more
wiley +1 more source
Elliptic-Curve Cryptography Implementation on RISC-V Processors for Internet of Things Applications
Elliptic-curve cryptography (ECC) is a popular technique of public-key cryptography used for secure communications in Internet of Things (IoT) applications.
Preethi Preethi +5 more
doaj +1 more source
EMSA5: A RISC-V Processor System for Enhanced Functional Safety in Embedded Applications
The RISC-V RV32 processor system EMSA5 was originally designed to meet the stringent requirements of functional safety as specified by ISO26262. It consists of a redundant multi-core architecture that supports advanced safety mechanisms such as Dual-Mode-
Faulwaßer, Michael, Zimmerling, Martin
core +1 more source
Decoding RNA regulation: Challenges and opportunities for RNA‐based therapies in Europe
Abstract RNA‐based medicinal products represent a promising frontier in personalised medicine, offering sequence‐specific disease targeting at various molecular levels, yet their clinical translation in the European Union (EU) may be hindered by regulatory uncertainty around definitions and evidence requirements; this study therefore aims to identify ...
Olivia C. Lewis +4 more
wiley +1 more source
Optimizing TLS Cryptographic Operations on RISC-V SoC with OpenTitan RoT [PDF]
This work presents a preliminary evaluation of a cryptographic software stack leveraging OpenTitan as a hardware security module within a RISC-V-based system-on-chip.
Edoardo Patti +6 more
core

