Results 91 to 100 of about 10,270,316 (283)
Re‐Thinking Electronic Circuit Design Through Emerging Reconfigurable Field Effect Transistors
Advanced Science, EarlyView.Graphical illustration of reconfigurable field effect transistor (RFET) operation modes, including n‐type, p‐type, and ambipolar transport, as well as their areas of application discussed in this review: digital circuit design, analog circuit design, post‐Shannon computing, and sensing. ABSTRACT Reconfigurable field‐effect transistors, short RFETs, are
Jens Trommer +19 more
wiley +1 more source
Discover ComputingThis paper presents the design and evaluation of a light-weight RISC-V-based microcontroller targeted for embedded and real-time applications. Leveraging the modularity and openness of the RISC-V instruction set architecture (ISA), the proposed single ...
Rachit Srivastava +4 more
doaj +1 more source
Optimizing TLS Cryptographic Operations on RISC-V SoC with OpenTitan RoT [PDF]
This work presents a preliminary evaluation of a cryptographic software stack leveraging OpenTitan as a hardware security module within a RISC-V-based system-on-chip.
Edoardo Patti +6 more
core
, 2016 This bachelor thesis deals with the implementations of RISC-V processor model in the language for architecture description CodAL. The theoretical part of thesis is focused on the description of CodAL language and classification of processors.
Nosterský, Milan
core +2 more sources
Heterogeneous computing at INFN-T1 [PDF]
EPJ Web of ConferencesAt INFN-T1 we recently acquired some nodes with ARM and RISC-V CPUs to understand the experiment level of readiness on new hardware solutions and to test our production pipelines. After some initial testing, ARM resources entered the standard farm, since
Chierici Andrea +4 more
doaj +1 more source
RISC-V CO-PROCESSOR UNIT FOR IMNPU SPECIFICATIONS, FUNCTIONAL SAFE RISC-V HOST CORE SPECIFICATIONS
, 2023 The objective of deliverable 3.1 (D3.1) “RISC-V co-processor unit for IMNPU specifications, functional safe RISC-V host core specifications” is to define and provide the specifications of the two RISC-V based components in the NeuroSoC system: - the RISC-
Daniel Gracia Pérez +1 more
core +1 more source
Three-Stage Pipelined RISC-V Processor Core with Data Forwarding [PDF]
ITM Web of ConferencesRISC-V has emerged as the most popular open-source instruction set architecture for embedded systems, edge computing, and academic prototyping and research due to its simplicity, modularity, and lack of licensing fees.
Xie Mingjun
doaj +1 more source
, 2023 V této práci jsme přidali podporu RISC-V do emulátoru MSIM. MSIM podporoval pouze procesor MIPS R4000 a byl používán pro výuku operačních systémů. Tento projekt přepracovává MSIM aby podporoval více architektur procesoru a přidává implementaci procesoru ...
Papesch, Jan
core
Validating Full-System RISC-V Simulator: A Systematic Approach [PDF]
RISC-V-based Systems-on-Chip (SoCs) are witnessing a steady rise in adoption in both industry and academia. However, the limited support for Linux-capable Full System-level simulators hampers development of the RISC-V ecosystem.
Atienza Alonso, David +4 more
core
Elliptic-Curve Cryptography Implementation on RISC-V Processors for Internet of Things Applications
Journal of EngineeringElliptic-curve cryptography (ECC) is a popular technique of public-key cryptography used for secure communications in Internet of Things (IoT) applications.
Preethi Preethi +5 more
doaj +1 more source