goSLP: globally optimized superword level parallelism framework [PDF]
Proc. ACM Program. Lang., 2018 Modern microprocessors are equipped with single instruction multiple data (SIMD) or vector instruction sets which allow compilers to exploit superword level parallelism (SLP), a type of fine-grained parallelism.
Charith Mendis, Saman P. Amarasinghe
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Topic 8 Parallel Computer Architecture and Instruction-Level Parallelism [PDF]
, 2003 Parallel computer architecture and instruction-level parallelism are hot topics at Euro-Par conferences, since these techniques are present in most contemporary computing systems. At Euro-Par 2003, 18 papers were submitted to the topic, from which 1 distinguished, 4 regular and 4 short papers were accepted.
Stamatis Vassiliadis +3 more
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Software thread integration for instruction-level parallelism [PDF]
ACM Transactions on Embedded Computing Systems, 2013 Multimedia applications require a significantly higher level of performance than previous workloads of embedded systems. They have driven digital signal processor (DSP) makers to adopt high-performance architectures like VLIW (Very-Long Instruction Word).
Won So, Alexander G. Dean
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Exploiting Thread-Level and Instruction-Level Parallelism to Cluster Mass Spectrometry Data using Multicore Architectures. [PDF]
Netw Model Anal Health Inform Bioinform, 2014 Saeed F +3 more
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Employing register channels for the exploitation of instruction level parallelism [PDF]
ACM SIGPLAN Notices, 1990 A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the use of shared register channels as the communication mechanism among processors in a multiprocessor chip.
Rajiv Gupta
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Increasing Instruction-Level Parallelism with Instruction Precomputation [PDF]
, 2002 Value reuse improves a processor’s performance by dynamically caching the results of previous instructions and reusing those results to bypass the execution of future instructions that have the same opcode and input operands. However, continually replacing the least recently used entries could eventually fill the value reuse table with instructions ...
Joshua J. Yi +2 more
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Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism [PDF]
, 2022 Exploiting instruction level parallelism (ILP) is a widely used method for increasing performance of processors. While traditional very long instruction word (VLIW) processors can exploit ILP energy-efficiently thanks to static instruction scheduling, they suffer from bad code density with serial parts that cannot utilize the multi-issue capabilities ...
Kari Hepola +2 more
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Instruction-Level Parallelism and Uniprocessor Architecture [PDF]
, 1999 Research in Instruction-Level Parallelism (ILP) is concerned with architectural innovations in the processor to expose parallelism between the execution of instructions. Of course, the relationship with the research on the memory hierarchy and on compiler optimisation techniques is very strong.
Pascal Sainrat, Mateo Valero
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Realizing the Calculation of a Fully Normalized Associated Legendre Function Based on an FPGA [PDF]
SensorsA large number of fully normalized associated Legendre function (fnALF) calculations are required to compute Earth’s gravity field elements using ultra high-order gravity field coefficient models.
Yuxiang Fang, Qingbin Wang, Yichao Yang
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Exploiting instruction level parallelism in processors by caching scheduled groups [PDF]
Conference Proceedings. The 24th Annual International Symposium on Computer Architecture, 1997 Ravi Nair, Martin Hopkins
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