Results 11 to 20 of about 220,437 (272)
Available instruction-level parallelism for superscalar and superpipelined machines [PDF]
ACM SIGARCH Computer Architecture News, 1989 Superscalar machines can issue several instructions per cycle. Superpipelined machines can issue only one instruction per cycle, but they have cycle times shorter than the latency of any functional unit. In this paper these two techniques are shown to be roughly equivalent ways of exploiting instruction-level parallelism. A parameterizable
Norman P. Jouppi, D. W. Wall
semanticscholar +4 more sources
goSLP: Globally Optimized Superword Level Parallelism Framework [PDF]
Proc. ACM Program. Lang., 2018 Modern microprocessors are equipped with single instruction multiple data (SIMD) or vector instruction sets which allow compilers to exploit superword level parallelism (SLP), a type of fine-grained parallelism.
Amarasinghe, Saman, Mendis, Charith
core +2 more sources
PerPI: A Tool to Measure Instruction Level Parallelism [PDF]
Workshop on Applied Parallel Computin, 2012 We introduce and describe PerPI, a software tool analyzing the instruction level parallelism (ILP) of a program. ILP measures the best potential of a program to run in parallel on an ideal machine – a machine with infinite resources. PerPI is a programmer-oriented tool the function of which is to improve the understanding of how the algorithm and the ...
Goossens, Bernard +3 more
openaire +3 more sources
Exploiting Thread-Level and Instruction-Level Parallelism to Cluster Mass Spectrometry Data using Multicore Architectures. [PDF]
Netw Model Anal Health Inform Bioinform, 2014 Saeed F +3 more
europepmc +3 more sources
Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism [PDF]
, 2022 Exploiting instruction level parallelism (ILP) is a widely used method for increasing performance of processors. While traditional very long instruction word (VLIW) processors can exploit ILP energy-efficiently thanks to static instruction scheduling, they suffer from bad code density with serial parts that cannot utilize the multi-issue capabilities ...
Kari Hepola +2 more
openalex +4 more sources
Hacky Racers: Exploiting Instruction-Level Parallelism to Generate Stealthy Fine-Grained Timers [PDF]
International Conference on Architectural Support for Programming Languages and Operating Systems, 2023 Side-channel attacks pose serious threats to many security models, especially sandbox-based browsers. While transient-execution side channels in out-of-order processors have previously been blamed for vulnerabilities such as Spectre and Meltdown, we show
Haocheng Xiao, Sam Ainsworth
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The Future of Instruction-Level Parallelism (ILP) [PDF]
High-performance processors have long used instruction-level parallelism (ILP) to achieve performance, but in the past decade processor vendors have dramatically increased their reliance upon this technique. We therefore take another look at the theoretical limits of ILP, in order to evaluate challenges and opportunities for processor architectures ...
Chadwick, Alexandra W +5 more
openaire +4 more sources
Instruction-Level Parallelism and Uniprocessor Architecture [PDF]
, 1999 Research in Instruction-Level Parallelism (ILP) is concerned with architectural innovations in the processor to expose parallelism between the execution of instructions. Of course, the relationship with the research on the memory hierarchy and on compiler optimisation techniques is very strong.
Pascal Sainrat, Mateo Valero
openalex +3 more sources
Realizing the Calculation of a Fully Normalized Associated Legendre Function Based on an FPGA [PDF]
SensorsA large number of fully normalized associated Legendre function (fnALF) calculations are required to compute Earth’s gravity field elements using ultra high-order gravity field coefficient models.
Yuxiang Fang, Qingbin Wang, Yichao Yang
doaj +2 more sources
An efficient global resource constrained technique for exploiting instruction level parallelism [PDF]
, 1992 A new Global Resource-constrained Percolation (GRiP) scheduling technique is presented for exploiting instruction level parallelism. Other techniques that have been proposed either have been prohibitively expensive in terms of computation or have limited
Alexandru Nicolau, Steven Novack
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