Results 31 to 40 of about 189,345 (270)
PerPI: A Tool to Measure Instruction Level Parallelism
Workshop on Applied Parallel Computin, 2010 Bernard Goossens +3 more
semanticscholar +3 more sources
goSLP: globally optimized superword level parallelism framework [PDF]
Proc. ACM Program. Lang., 2018 Modern microprocessors are equipped with single instruction multiple data (SIMD) or vector instruction sets which allow compilers to exploit superword level parallelism (SLP), a type of fine-grained parallelism.
Charith Mendis, Saman P. Amarasinghe
semanticscholar +1 more source
LLVM RISC-V RV32X Graphics Extension Support and Characteristics Analysis of Graphics Programs
IEEE Access, 2023 In recent years, virtual reality technology has become the dominant means of human-computer interaction, with computer graphics rendering technology being a crucial component in realizing virtual reality experiences.
Peng Wang, Zhi-Bin Yu
doaj +1 more source
Optimized Realization of Sobel Edge Detection Algorithm for FT-M7002 [PDF]
Jisuanji gongcheng, 2022 Edge detection is a robust image analysis method used in image processing and computer vision.The Sobel operator is widely used in edge detection and image processing.With the development of domestic FT series high-performance Digital Signal Processors ...
FAN Mingliang, GUO Zihan, CHAI Xiaonan, SHANG Jiandong
doaj +1 more source
Exploring Various Levels of Parallelism in High-Performance CRC Algorithms
IEEE Access, 2019 Modern processors have increased the capabilities of instruction-level parallelism (ILP) and thread-level parallelism (TLP). These resources, however, typically exhibit poor utilization on conventional cyclic redundancy check (CRC) algorithms.
Mucong Chi, Dazhong He, Jun Liu
doaj +1 more source
A Highly-Efficient and Tightly-Connected Many-Core Overlay Architecture
IEEE Access, 2021 The technology advances of CPU (Central Processing Unit) architecture alternate between generalization and specialization. In the past decade, the general performance has been enhanced while addressing the new brick walls that include power, memory, and ...
Riadh Ben Abdelhamid +2 more
doaj +1 more source
Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy Optimization
IEEE Access, 2020 Evolution of semiconductor manufacturing technology leads to the rising trend of leakage current and the end of Dennard scaling. At the dark silicon era, aggressive power gating scheme with quantitative management on power-gated hardware resources is ...
Yung-Cheng Ma
doaj +1 more source
Design and Implementation of SIMD Unaligned Memory Access Structure [PDF]
Jisuanji gongcheng, 2016 Single Instruction Multiple Data(SIMD) is an effective approach to realize data level parallelism,but accessing unaligned data seriously affects vectorization of the program and causes processor performance degradation.In order to reduce the latency of ...
YU Chenglong,WANG Yongwen
doaj +1 more source
Evaluation Method Based on FPGA Emulation for Resistive Neural Network Accelerators [PDF]
Jisuanji gongcheng, 2021 The Processing-in-Memory(PIM) neural network accelerators based on resistive devices require careful simulation and evaluation during the early stage of architecture design, which ensures the accuracy of neural networks to meet the requirements of design.
SHI Yongquan, JING Naifeng
doaj +1 more source
CAAI Transactions on Intelligence Technology, EarlyView., 2023 Abstract This research focuses on addressing the privacy issues in healthcare advancement monitoring with the rapid establishment of the decentralised communication system in the Internet of Medical Things (IoMT). An integrated blockchain homomorphic encryption standard with an in‐build supervised learning‐based smart contract is designed to improvise ...
Chandramohan Dhasarathan +7 more
wiley +1 more source