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Protean: Resource-efficient Instruction Prefetching [PDF]
Proceedings of the International Symposium on Memory Systems, 2023 FunderElectronics and Telecommunications Research Institute (ETRI)Grant number ...
Muhammad Hassan +2 more
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Effective Instruction Prefetching via Fetch Prestaging [PDF]
19th IEEE International Parallel and Distributed Processing Symposium, 2005 As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher miss rate) or large caches with a pipelined access (with higher branch misprediction penalty).
Ayose Falcón, A. Ramirez, Mateo Valero
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Fetch-Directed Instruction Prefetching Revisited [PDF]
, 2020 Prior work has observed that fetch-directed prefetching (FDIP) is highly effective at covering instruction cache misses. The key to FDIP's effectiveness is having a sufficiently large BTB to accommodate the application's branch working set. In this work, we introduce several optimizations that significantly extend the reach of the BTB within the ...
Truls Asheim, Rakesh Kumar, Boris Grot
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Kilo-instruction processors, runahead and prefetching [PDF]
Proceedings of the 3rd conference on Computing frontiers, 2006 There is a continuous research effort devoted to overcome the memory wall problem. Prefetching is one of the most frequently used techniques. A prefetch mechanism anticipates the processor requests by moving data into the lower levels of the memory hierarchy. Runahead mechanism is another form of prefetching based on speculative execution.
Tanausú Ramírez +3 more
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Lockup-free instruction fetch/prefetch cache organization [PDF]
25 years of the international symposia on Computer architecture (selected papers), 1998 In the past decade, there has been much literature describing various cache organizations that exploit general programming idiosyncrasies to obtain maximum hit rate (the probability that a requested datum is now resident in the cache). Little, if any, has been presented to exploit: (1) the inherent dual input nature of the cache and (2) the many-datum ...
David Kroft
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Execution history guided instruction prefetching [PDF]
Proceedings of the 16th international conference on Supercomputing, 2002 zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Yi Zhang, Steve Haga, Rajeev Barua
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Combining instruction prefetching with partial cache locking to improve WCET in real-time systems. [PDF]
PLoS One, 2013 Ni F, Long X, Wan H, Gao X.
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Method of Timing Attack for Linux Against KASLR [PDF]
Jisuanji gongcheng, 2021 For Linux systems with Kernel Address Space Layout Randomization(KASLR) protection, this paper proposes a Cache instant attack method based on CPU prefetch instruction.
CONG Mou, ZHANG Ping, WANG NING
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Hierarchical Prefetching: A Software-Hardware Instruction Prefetcher for Server Applications
Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2Tingji Zhang +9 more
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Morrigan: A Composite Instruction TLB Prefetcher [PDF]
MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021 The effort to reduce address translation overheads has typically targeted data accesses since they constitute the overwhelming portion of the second-level TLB (STLB) misses in desktop and HPC applications. The address translation cost of instruction accesses has been relatively neglected due to historically small instruction footprints.
Vavouliotis, Georgios +4 more
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