Results 91 to 100 of about 248 (147)
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Composite Instruction Prefetching: Combining Complementary Instruction Prefetchers
IEEE International Conference on Computer Design (ICCD), 2022Chacon, Gino +6 more
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Retrospective: lockup-free instruction fetch/prefetch cache organization
25 years of the international symposia on Computer architecture (selected papers), 1998 David Kroft
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Instruction prefetching using branch prediction information
Proceedings International Conference on Computer Design VLSI in Computers and Processors, 2002Instruction prefetching can effectively reduce instruction cache misses, thus improving the performance. In this paper, we propose a prefetching scheme, which employs a branch predictor to run ahead of the execution unit and to prefetch potentially useful instructions.
null I-Cheng K. Chen +2 more
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On instruction and data prefetch mechanisms
1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers, 2002Cache misses are becoming relatively more expensive in modern processors. This is largely due do the fact that processor clock rates are increasing faster than the latency of main memory is improving. Prefetch has been used to hide memory latency. There are at least two kinds of prefetches - automatic prefetch and instruction-initiated prefetch.
H.C. Young +4 more
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Instruction cache prefetching directed by branch prediction
IEE Proceedings - Computers and Digital Techniques, 1999As the gap between processor speed and memory speed grow, so the performance penalty of instruction cache misses gets higher. Instruction cache prefetching is a technique to reduce this penalty. The prefetching methods determine the target line to be prefetched generally based on the current fetched line address.
J. -C. Chiu +3 more
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A Hardware Prefetching Mechanism for Vector Gather Instructions
2019 IEEE/ACM 9th Workshop on Irregular Applications: Architectures and Algorithms (IA3), 2019Vector gather instructions are responsible for handling indirect memory accesses in vector processing. Since the indirect memory accesses usually express irregular access patterns, they have relatively low spatial and temporal locality compared with regular access patterns.
Hikaru Takayashiki +3 more
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Efficient line buffer instruction cache scheme with prefetch
Proceedings of the 2nd International Conference on Interaction Sciences: Information Technology, Culture and Human, 2009Cache is an important component of modern processor. On chip instruction cache can comprise one third of CPU power. So both the energy efficiency and performance should be concerned when designing processors. Line buffer cache architecture, which adds a line size buffer between Level 1 cache and IU (integer unit), has the advantage of low energy ...
Weili Li, Lixin Yu
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A distributed logic program instruction prefetching scheme
Microprocessing and Microprogramming, 1987Abstract An instruction issue system is described, developed for application in microcomputer design in order to minimize the data transmission expense between storage and cpu , and thus reducing hardware costs. It consists of a program storage module endowed with some processing capabilities, and an intermediate sequential storage system for the ...
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Fetch directed instruction prefetching
MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, 2003G. Reinman, B. Calder, T. Austin
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Wrong-path instruction prefetching
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29, 2002J. Pierce, T. Mudge
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