Results 11 to 20 of about 248 (147)

PDIP: Priority Directed Instruction Prefetching

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2
Bhargav Reddy Godala, S. Ramesh, Gilles Pokam, Jared Stark, André Seznec, Dean M. Tullsen, David I. August   +6 more
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The Entangling Instruction Prefetcher [PDF]

IEEE Computer Architecture Letters, 2020
Prefetching instructions is a fundamental technique for designing high-performance computers. There are three key properties to consider when designing an efficient and effective prefetcher: timeliness, coverage, and accuracy. Timeliness is an essential property, as bringing instructions too early increases the risk of the instructions being evicted ...
Alberto Ros, Alexandra Jimborean
openaire   +2 more sources

Prefetching for the Kilo-Instruction Processor

, 2015
The large latency of memory accesses in modern computer systems is a key obstacle to achieving high processor utilization. Techniques to reduce or tolerate large memory latencies become essential for achieving high processor utilization. Prefetch is one of the most widely studied mechanisms at literature.
Matherey Bracamonte Nunez
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Neighborhood prefetching on multiprocessors using instruction history [PDF]

Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622), 2002
D.M. Koppelman
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MANA: Microarchitecting an Instruction Prefetcher

, 2021
24 pages with 15 ...
Ansari, Ali, Golshan, Fatemeh, Lotfi-Kamran, Pejman, Sarbazi-Azad, Hamid   +3 more
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Hardware Support for Prescient Instruction Prefetch [PDF]

10th International Symposium on High Performance Computer Architecture (HPCA'04), 2004
This paper proposes and evaluates hardware mechanisms for supporting prescient instruction prefetch — an approach to improving single-threaded application performance by using helper threads to perform instruction prefetch. We demonstrate the need for enabling store-to-load communication and selective instruction execution when directly pre-executing ...
T.M. Aamodt, P. Chow, P. Hammarlund, Hong Wang, J.P. Shen   +4 more
openaire   +1 more source

Efficient Prefetch and Issue Scheduling Approaches for Simultaneous Multithreading Applied to Superscalar RISC-V Processor

IEEE Access
Thread level parallelism (TLP) is a common approach to achieve parallelism where Instruction level parallelism (ILP) is insufficient. Hardware multithreading is a prevalent approach in the micro-architecture layer for tolerating long events such as ...
Hananya Ribo, Shlomo Greenberg
doaj   +1 more source

Optimizing Lattice Basis Reduction Algorithm on ARM V8 Processors

Applied Sciences
The LLL (Lenstra–Lenstra–Lovász) algorithm is an important method for lattice basis reduction and has broad applications in computer algebra, cryptography, number theory, and combinatorial optimization.
Ronghui Cao, Julong Wang, Liming Zheng, Jincheng Zhou, Haodong Wang, Tiaojie Xiao, Chunye Gong   +6 more
doaj   +1 more source

A Cost-Effective Entangling Prefetcher for Instructions

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021
Prefetching instructions in the instruction cache is a fundamental technique for designing high-performance computers. There are three key properties to consider when designing an efficient and effective prefetcher: timeliness, coverage, and accuracy.
Ros, Alberto, Jimborean, Alexandra
openaire   +2 more sources

A cycle-level recovery method for embedded processor against HT tamper. [PDF]

Heliyon, 2023
Zhou W, Ye KH, Yuan S, Li L.
europepmc   +1 more source